In the three-dimensional view of a silicon n-channel MOS transistor

Introductory Circuit Analysis (13th Edition)
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Author:Robert L. Boylestad
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In the three-dimensional view of a silicon n-channel MOS transistor
shown below, S = 20 nm. The transistor is of width 1μm. The
depletion width formed at every p-n junction is 10 nm. The relative
permittivity of Si and SiO2, respectively, are 11.7 and 3.9, and
E0 = 8.9 × 10-¹2 F/m
0.2μm
0.2μm
p substrate
B
•G
|1nm
0.2μm
1um
0.2μm
The gate- source overlap capacitance is approximately.
1um
Transcribed Image Text:In the three-dimensional view of a silicon n-channel MOS transistor shown below, S = 20 nm. The transistor is of width 1μm. The depletion width formed at every p-n junction is 10 nm. The relative permittivity of Si and SiO2, respectively, are 11.7 and 3.9, and E0 = 8.9 × 10-¹2 F/m 0.2μm 0.2μm p substrate B •G |1nm 0.2μm 1um 0.2μm The gate- source overlap capacitance is approximately. 1um
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