In the figure below, assume that the 4-bit registers and the D-FF are initialized as follows: RegA = 9. RegB=4, Q=1, all data is in Decimal (unsigned) Then all registers are put in shift-right mode and 4 clock pulses are entered. What is the final unsigned decimal value in RegA register? Note: write your answer in decimal, not in binary SI Shift control SO Rega CLK X Y FA Z SO Answer: RegB Set QD S C

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In the figure below, assume that the 4-bit registers and the D-FF are initialized as follows:
RegA = 9. RegB = 4, Q=1, all data is in Decimal (unsigned)
Then all registers are put in shift-right mode and 4 clock pulses are entered.
Ache
What is the final unsigned decimal value in RegA register?
Note: write your answer in decimal, not in binary
SI
Shift
control
SO
RegA
CLK
X
Y FA
SO
Answer:
SI
RegB
Set
N
QD
S
C
Transcribed Image Text:In the figure below, assume that the 4-bit registers and the D-FF are initialized as follows: RegA = 9. RegB = 4, Q=1, all data is in Decimal (unsigned) Then all registers are put in shift-right mode and 4 clock pulses are entered. Ache What is the final unsigned decimal value in RegA register? Note: write your answer in decimal, not in binary SI Shift control SO RegA CLK X Y FA SO Answer: SI RegB Set N QD S C
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