In a three level memory hierarchy, the access time of cache, main and virtual memory is 5 nano-seconds, 100 nano-seconds and 10 milli- seconds respectively. If the hit ratio is 80% for the cache and 99.5% for the main memory, then the closest average access time of memory nierarchy in nano-seconds is:
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![In a three level memory hierarchy, the access
time of cache, main and virtual memory is
nano-seconds, 100 nano-seconds and 10 milli-
seconds respectively. If the hit ratio is 80% for
the cache and 99.5% for the main memory, then
the closest average access time of memory
hierarchy in nano-seconds is:](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F1c9f2459-56b2-4108-87bd-c9f6b067d088%2F1c14ac7e-6812-458e-b91b-6eae310c0524%2Fcsi5q7_processed.jpeg&w=3840&q=75)
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- In a two-level cache system, the access time of cache L₁ is 2 cycle and the access time of cache L2 is 7 cycle. The miss rate of L₁ is thrice the miss rate of L2. the miss penalty from the L2 cache to main memory is 20 clock cycles. The average memory access time of the system is 4 cycle. The hit rate of L2 is (correct up to 2 decimal places).A computer system has a memory access time of 120 ns. The hit rate is 96% and memory and cache accesses don' t lap and affect each other. In order AMAT to be under 12 ns, what should the maximum cache access time be?A cache memory has a line size of eight 64-bit words and a capacity of 4K words. The main memory size that is cacheable is 1024 Mbits. Assuming 4-way set associative mapping and that the addressing is done at the byte level. What is the format of the main memory addresses (i.e s-d, d, and w)? For the hexadecimal main memory location 2BFACEDH, find the corresponding 4-way set-associative memory format
- A computer system has an L1 cache, an L2 cache, and a main memory unit 10.4k view= connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds, 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and the main memory unit respectively. Data Data Bus Bus L1 L2 Main Cache Cache Memory 4 words 4 words When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?A memory hierarchy contains a single cache with a miss rate of 2% that holds both instructions and data. The miss penalty to access main memory is 100 cycles. 15% of the instructions are jumps, 20% are stores, 20% are loads (30% have values used in the next instruction), 10% are branches (taken 20% of the time), and 35% are ALU instructions. Jumps and branches are determined in the ID stage. What is the base CPI, and what is the effective CPI?Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?
- Assume the miss rate of an instruction cache is 4% and the miss rate of the data cache is 5%. If a processor has a CPI of 3 without any memory stalls, and the miss penalty is 50 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 44%.A certain processor uses separate instruction and data caches with hit ratios 97% and 94% respectively. The access time from the processor to either cache is 1 clock cycle, and the block transfer time between the caches and main memory is 67 clock cycles. Among blocks replaced in the data cache, 21% is the percentage of dirty blocks (Dirty means that the cache copy is different from the memory copy). Assuming a write-back policy, what is the AMAT for the instructions in this system? Round to 2 decimal places.A cache has a hit time Tc = 2 cycles and a miss rate Pmiss = 0.04. The main memory access time is Tmm = 36 cycles. The data-cache and instruction-cache have identical performance. A program has the following instruction distribution: probability of 0.3 for R-type instructions, 0.2 for load, 0.1 for store, and others for control instructions. Assume control instructions do not cause any loss. The processor is running at 1 GHz. Evaluate the average access time in nano-seconds of the memory system.
- Suppose a byte-addressable computer using set associative cache has 224 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?Suppose the cache access time is 1 ns, main memory access time is 100 ns and the cache hit rate is 98%. Assuming memory access is initiated with cash access, what is the effective memory access time (round up to 2 digits after the decimal point)Design the memory mapping between the Cache memory of 512 MB to the mainmemory of 4 GB using 4 way set associative method where the block size is of 1 MB.Consider each memory location is byte addressable.
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