1.) We examine how pipelining affects the clock cycle time of the processor. assume that individual stages of the datapath have the following latencies:IFIDEXMEMWB150 ps100 ps150 ps200 ps100 psWhat is the clock cycle of a pipelined processor (assume no stall or hazard)?options: 100 ps 200 ps 700 ps 150 ps2.) Individual stages of the datapath have the following latencies:IFIDEXMEMWB150 ps100 ps150 ps200 ps100 psWhat is the total latency of five LW instructions in a pipelined processor (assume no stalls or hazards)?options: 1800 ps 2000 ps 2400 ps 1600 ps

Here in this question we have given a five stage pipeline.and we have asked how pipelining affects…

Answered: ID EX MEM WB 150 ps 100 ps 150 ps…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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1.) We examine how pipelining affects the clock cycle time of the processor. assume that individual stages of the datapath have the following latencies:

IF	ID	EX	MEM	WB
150 ps	100 ps	150 ps	200 ps	100 ps

What is the clock cycle of a pipelined processor (assume no stall or hazard)?

options:

	100 ps
	200 ps
	700 ps
	150 ps

2.) Individual stages of the datapath have the following latencies:

IF	ID	EX	MEM	WB
150 ps	100 ps	150 ps	200 ps	100 ps

What is the total latency of five LW instructions in a pipelined processor (assume no stalls or hazards)?

options:

	1800 ps
	2000 ps
	2400 ps
	1600 ps

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