How would I translate this c++ code into assembly? Done on CCS for MSP432
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- Given the following timing waveform for Y, draw D and E. 10ns 13ns Sns 10ns 2ns 10 20 30 40 50 wire #3 D; // net delay on wire D assign #5 D - Y; // statement 1 - inertial delay wire #5 E; // net delay on wire E assign #3 E = Y; // statement 1 inertial delayon on on on A 4-bit carry look-ahead adder and a 64-bit carry look-ahead adder have the same complexity Select one: O True O False Select the correct answer of the BCD addition of: 205+147 Select one: O a. 001101010010 O b. 110001110101 O c. 100111110101 O d. 100001111101 Verilog is a hardware descriptive language that is easier than VHDL. Select one: O True O False In VHDL, a signal's name can only start and contain characters. Select one: O True O False• A circuit that controls a given digital system has three inputs: X₁, X₂, and X3. It has to recognize three different conditions: • Condition A is true if x3 is true and either x₁ is true or x₂ is false • Condition B is true ifx, is true and either x₂ or x3 is false • Condition C is true if x₂ is true and either x, is true or x3 is false • The control circuit must produce an output of 1 if at least two of the conditions A, B, and C are true. Design the simplest circuit that can be used for this purpose. A=X3(x₁+x₂) = X3X₁ + X3X2 B = x₁(x₂ + x3) = X₁ X₂ + X₁ X3 C = x₂(x₁+x3) = X₂X₁ + X₂ X3 f = AB + AC + BC = x₁(x3 + x₂)
- Task 1 Construct 8-bit input encoder by using Verilog language and then create appropriate circuit. Task 2 Construct testbench for 8-bit input encoder from task 1 by using Verilog language and then create appropriate circuit.Data inputs DODID2 D3 LOAD DO D1 D2 J D3 CLK D/Ū Z CTEN CTEN- MAX CTR DIV 10 MIN 74190 LOAD CLK C PRCO QOQ1Q2Q3 Data outputs MAX/MIN RCO IA Figure 8-5 What function will the counter shown in Figure 8-5 be performing during period B on the timing diagram? Inhibited O Counting up OLoading O Counting down Data Inputs Data outputsAn 8 x 1 multiplexer has inputs A , B , and C connected to the selection inputs S2 , S1 , andS0 , respectively. The data inputs I0 through I7 are as follows:(a) I1 I2 I7 0; I3 I5 1; I0 I4 D ; and I6 D ’.(b) I1 I2 0; I3 I7 1; I4 I5 D ; and I0 I6 D ’.Determine the Boolean function that the multiplexer implements.
- the following combinational circuit takes two 4-bit numbers( A , B) and takes a single bit control inputFigure shows how a 2x2 crossbar can be implemented using 2-to-1 multiplexers. The multiplexer select inputs are controlled by the signal s. If s = 0 then... X1 y1 1 S X2 – y2 1 a. the crossbar connects x1 to y1 and x2 to y2 b. the crossbar connects x¡ to y2 and x2 to y1design the 8-bit Function Unit Combining Arithmetic Logic Unit (ALU) and a Shifter that can perform the operations given in table 1 below
- A counter circuit is shown in the figure. The counter counts as Q1 QO Vpp J Q Q Clock K K O a. QOQ1: 11 --> 00 --> 10 --> 01 --> 11 O b. QOQ1:00 --> 01 --> 10 -->11 --> 00 O c. QOQ1: none of these O d. QOQ1: 11 --> 01 --> 10 --> 00 --> 11 Cl* the state diagram for the following timing diagram is CK a/1 /PS Z e/0 a/1 b/0 f/1 0/p c/0 e/1 c/0 0/P B O A 1 a/1 g/0 b/0 f/1 1 e/1 c/0 1 d/0 None of the above O CDesign and draw a circuit diagram for a multiplexer for 2 inputs, x0 and x1, and one control bit, c0. When the control bit is 0, then the circuit should give x0 as output. When the control bit is 1, the output should be x1. Design a multiplexer for 4 inputs, x0, x1, x2, and x3, and 2 control bits, c0 and c1. The output for the multiplexer should be xk, whenever k = c1c0.