Given the Verilog skeleton code given in the example document for this quiz. Replace and with the code below and determine y_tb and z_tb at the time stated. y = -a & -b; z = a | c; a_tb = 1; b_tb = 1; c_tb= 1; #10 a_tb = 0; #20 b_tb = 0; Find y_tb and z_tb at time 25. O a. y_tb = 0, z_tb = 0 O b.y_tb = 0, z_tb = 1 O c. y_tb = 1, z_tb = 0 Q d.y_tb = 1, z_tb = 1

Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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Given the Verilog skeleton code in the example document for this quiz, replace `<logic in device under test>` and `<test vector sequence>` with the code below and determine `y_tb` and `z_tb` at the time stated.

```verilog
<logic in device under test>
y = ~a & ~b;
z = a | c;

<test vector sequence>
a_tb = 1;
b_tb = 1;
c_tb = 1;
#10 a_tb = 0;
#20 b_tb = 0;
```

Find `y_tb` and `z_tb` at time 25.

- a. y_tb = 0, z_tb = 0
- b. y_tb = 0, z_tb = 1
- c. y_tb = 1, z_tb = 0
- d. y_tb = 1, z_tb = 1
Transcribed Image Text:Given the Verilog skeleton code in the example document for this quiz, replace `<logic in device under test>` and `<test vector sequence>` with the code below and determine `y_tb` and `z_tb` at the time stated. ```verilog <logic in device under test> y = ~a & ~b; z = a | c; <test vector sequence> a_tb = 1; b_tb = 1; c_tb = 1; #10 a_tb = 0; #20 b_tb = 0; ``` Find `y_tb` and `z_tb` at time 25. - a. y_tb = 0, z_tb = 0 - b. y_tb = 0, z_tb = 1 - c. y_tb = 1, z_tb = 0 - d. y_tb = 1, z_tb = 1
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