6 7 8 9 10 11 2 Testbench Code timescale ins / ips 3 module counter_tb; 4 5 reg clk_TB; reg RESET_TB; wire [3:0] Count; counter uut ( .clk (clk_TB), .RESET (RESET_TB), 12 .Count (Count) 13 ); 14 150 initial begin 16 17 18 end 19 20 21 22 clk_TB = 0; forever #10 clk_TB = -clk_TB; initial begin RESET TB-02 #20; 23 RESET TB 1; 24 #100; 25 $finish; 26 end 27 28 endmodule Given the Verilog code for a counter and the corresponding testbench code, complete the timing diagram plot for the clock, reset, and output (as a vector). The counter increments on each clock pulse. Along with the plot of Q over time, write the corresponding count values in both binary and decimal above the plot. 2 3 12 Verilog Code `timescale ins / 1ps module counter ( 6 7 ); B 96 input wire elk, input wire RESET, output reg [3:0] Count always @(posedge clk or negedge RESET) begin if (-RESET) Count 4'b00101 else begin if (Count 14) Count 4'b0010; 15 16 else Count Count + 27 17 end 18 end 19 20 endmodule
6 7 8 9 10 11 2 Testbench Code timescale ins / ips 3 module counter_tb; 4 5 reg clk_TB; reg RESET_TB; wire [3:0] Count; counter uut ( .clk (clk_TB), .RESET (RESET_TB), 12 .Count (Count) 13 ); 14 150 initial begin 16 17 18 end 19 20 21 22 clk_TB = 0; forever #10 clk_TB = -clk_TB; initial begin RESET TB-02 #20; 23 RESET TB 1; 24 #100; 25 $finish; 26 end 27 28 endmodule Given the Verilog code for a counter and the corresponding testbench code, complete the timing diagram plot for the clock, reset, and output (as a vector). The counter increments on each clock pulse. Along with the plot of Q over time, write the corresponding count values in both binary and decimal above the plot. 2 3 12 Verilog Code `timescale ins / 1ps module counter ( 6 7 ); B 96 input wire elk, input wire RESET, output reg [3:0] Count always @(posedge clk or negedge RESET) begin if (-RESET) Count 4'b00101 else begin if (Count 14) Count 4'b0010; 15 16 else Count Count + 27 17 end 18 end 19 20 endmodule
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
Related questions
Question
![6
7
8
9
10
11
2
Testbench Code
timescale ins / ips
3 module counter_tb;
4
5
reg clk_TB;
reg RESET_TB;
wire [3:0] Count;
counter uut (
.clk (clk_TB),
.RESET (RESET_TB),
12
.Count (Count)
13
);
14
150
initial begin
16
17
18
end
19
20
21
22
clk_TB = 0;
forever #10 clk_TB = -clk_TB;
initial begin
RESET TB-02
#20;
23
RESET TB 1;
24
#100;
25
$finish;
26
end
27
28 endmodule](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Ff0c7c0e9-1042-4b47-9e78-c6aaeaae6479%2F700ee514-3c9f-4fe7-95f0-ae7a5ef4ebad%2Fwtcl86_processed.png&w=3840&q=75)
Transcribed Image Text:6
7
8
9
10
11
2
Testbench Code
timescale ins / ips
3 module counter_tb;
4
5
reg clk_TB;
reg RESET_TB;
wire [3:0] Count;
counter uut (
.clk (clk_TB),
.RESET (RESET_TB),
12
.Count (Count)
13
);
14
150
initial begin
16
17
18
end
19
20
21
22
clk_TB = 0;
forever #10 clk_TB = -clk_TB;
initial begin
RESET TB-02
#20;
23
RESET TB 1;
24
#100;
25
$finish;
26
end
27
28 endmodule
![Given the Verilog code for a counter and the corresponding testbench code, complete the timing
diagram plot for the clock, reset, and output (as a vector). The counter increments on each clock
pulse.
Along with the plot of Q over time, write the corresponding count values in both binary and
decimal above the plot.
2
3
12
Verilog Code
`timescale ins / 1ps
module counter (
6
7
);
B
96
input wire elk,
input wire RESET,
output reg [3:0] Count
always @(posedge clk or negedge RESET) begin
if (-RESET)
Count 4'b00101
else begin
if (Count
14)
Count
4'b0010;
15
16
else
Count Count + 27
17
end
18
end
19
20
endmodule](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Ff0c7c0e9-1042-4b47-9e78-c6aaeaae6479%2F700ee514-3c9f-4fe7-95f0-ae7a5ef4ebad%2F9baskgh_processed.png&w=3840&q=75)
Transcribed Image Text:Given the Verilog code for a counter and the corresponding testbench code, complete the timing
diagram plot for the clock, reset, and output (as a vector). The counter increments on each clock
pulse.
Along with the plot of Q over time, write the corresponding count values in both binary and
decimal above the plot.
2
3
12
Verilog Code
`timescale ins / 1ps
module counter (
6
7
);
B
96
input wire elk,
input wire RESET,
output reg [3:0] Count
always @(posedge clk or negedge RESET) begin
if (-RESET)
Count 4'b00101
else begin
if (Count
14)
Count
4'b0010;
15
16
else
Count Count + 27
17
end
18
end
19
20
endmodule
Expert Solution
This question has been solved!
Explore an expertly crafted, step-by-step solution for a thorough understanding of key concepts.
Step by step
Solved in 2 steps with 1 images
Recommended textbooks for you
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Concepts of Database Management
Computer Engineering
ISBN:
9781337093422
Author:
Joy L. Starks, Philip J. Pratt, Mary Z. Last
Publisher:
Cengage Learning
Prelude to Programming
Computer Engineering
ISBN:
9780133750423
Author:
VENIT, Stewart
Publisher:
Pearson Education
Sc Business Data Communications and Networking, T…
Computer Engineering
ISBN:
9781119368830
Author:
FITZGERALD
Publisher:
WILEY