Figure 1(a) shows the circuit diagram for the two programs in Figure 1(b). Compare between the two programs in Figure 1(b), and explain at least TWO differences in detail.

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Figure 1(a) shows the circuit diagram for the two programs in Figure 1(b). Compare between the two programs in Figure 1(b), and explain at least TWO differences in detail.

VDD Target
2xAAA
10k
3x10k
(800kHz nom.)
100p
100n
RA1
RAD-
RA2
RA3
Os1
os2-
VD
RA4
CLR
56OR
Vss
RB7
RB6
RBS
RB4
RBO
S6OR
Vs
RB1
56OR
RB2
RB3
56OR
16LF84A
56OR
56OR
56OR
56OR
3mm lo current
Figure 1(a): Circuit diagram for Q1(b)
本
本
本
Transcribed Image Text:VDD Target 2xAAA 10k 3x10k (800kHz nom.) 100p 100n RA1 RAD- RA2 RA3 Os1 os2- VD RA4 CLR 56OR Vss RB7 RB6 RBS RB4 RBO S6OR Vs RB1 56OR RB2 RB3 56OR 16LF84A 56OR 56OR 56OR 56OR 3mm lo current Figure 1(a): Circuit diagram for Q1(b) 本 本 本
;Program 1 (a)
; Device: PIC16F84A
;Program 1 (b)
list p-16F84A
#include pl6F84a.inc
03
05
status
equ
equ
porta
trisa
00
org
bsf
equ
05
status, 5
trisb
start
portb
equ
06
clrf
trisb
equ
06
bcf
status, 5
portb
clrf
00
org
bsf
movlw
movwf
status, 5
b'00011111'
start
portb, 3
porta, 3
portb, 3
loop
bef
btfss
trisa
bsf
movlw
movwf
00
trisb
portb, 4
porta, 4
portb, 4
bef
bef
status, 5
00
btfss
movlw
bsf
porta
portb
movwf
movwf
loop
end
clrf
movf
porta
|loop
porta, 0
portb
loop
movwf
goto
end
Figure 1(b): Basic input/output programs
Transcribed Image Text:;Program 1 (a) ; Device: PIC16F84A ;Program 1 (b) list p-16F84A #include pl6F84a.inc 03 05 status equ equ porta trisa 00 org bsf equ 05 status, 5 trisb start portb equ 06 clrf trisb equ 06 bcf status, 5 portb clrf 00 org bsf movlw movwf status, 5 b'00011111' start portb, 3 porta, 3 portb, 3 loop bef btfss trisa bsf movlw movwf 00 trisb portb, 4 porta, 4 portb, 4 bef bef status, 5 00 btfss movlw bsf porta portb movwf movwf loop end clrf movf porta |loop porta, 0 portb loop movwf goto end Figure 1(b): Basic input/output programs
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