Figure 1.5(a) shows the Verilog implementation of a module digital_block with a clockinput clk, a 10-bit input n[9:0] and an output out.(i)Sketch a block diagram showing the function of digital_block.(ii) This circuit is driven by a 50MHZ clock signal and an input N as shown inFigure 1.5(b). Sketch the output signal Y. State any assumption used.1module digital block(clk, n, out);// clock signalinputinput (9:0]outputclk;n;out;reg [9:0]reg [5:0]cnt;regout, tick;1011initial v = 10 b0;initial cnt = 6'd49;1213always e (posedge clk)if (cnt == 6' de) begincnt <= 6'd49;tick <= 1'b13;endelse begin141516171819cnt <= cnt 1'b1:tick <= 1'be;endalways @ (posedge tick) beginif (v < 10'd999)V <= v + 1'b1;elsev = 10'do;out <= (v < n):end31endmoduleFigure 1.5(a)digital_block750Nn[9:0]250outEY4ms8ms50MHZclkFigure 1.5(b)2~~~ 22Mm m

Sequential Logic Circuits use flip-flops as memory elements and in which their output is dependent…

Figure 1.5(a) shows the Verilog implementation of a module digital_block with a clock input cik, a 10-bit input n[9:0] and an output out. ) Sketch a block diagram showing the function of digital_block. (i1) This circuit is driven by a 5OMHZ clock signal and an input N as shown in Figure 1.5(b). Sketch the output signal Y. State any assumption used.

Figure 1.5(a) shows the Verilog implementation of a module digital_block with a clock input cik, a 10-bit input n[9:0] and an output out. ) Sketch a block diagram showing the function of digital_block. (i1) This circuit is driven by a 5OMHZ clock signal and an input N as shown in Figure 1.5(b). Sketch the output signal Y. State any assumption used.

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Question

Figure 1.5(a) shows the Verilog implementation of a module digital_block with a clock
input clk, a 10-bit input n[9:0] and an output out.
(i)
Sketch a block diagram showing the function of digital_block.
(ii) This circuit is driven by a 50MHZ clock signal and an input N as shown in
Figure 1.5(b). Sketch the output signal Y. State any assumption used.
1
module digital block(clk, n, out);
// clock signal
input
input (9:0]
output
clk;
n;
out;
reg [9:0]
reg [5:0]
cnt;
reg
out, tick;
10
11
initial v = 10 b0;
initial cnt = 6'd49;
12
13
always e (posedge clk)
if (cnt == 6' de) begin
cnt <= 6'd49;
tick <= 1'b13;
end
else begin
14
15
16
17
18
19
cnt <= cnt 1'b1:
tick <= 1'be;
end
always @ (posedge tick) begin
if (v < 10'd999)
V <= v + 1'b1;
else
v = 10'do;
out <= (v < n):
end
31
endmodule
Figure 1.5(a)
digital_block
750
N
n[9:0]
250
outEY
4ms
8ms
50MHZ
clk
Figure 1.5(b)
2~~~ 22Mm m

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Step 1Sequential Logic Circuits

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Step 2Classification of Sequential Logic

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Step 3(i) Sketch a block diagram showing the function of digital_block.

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Step 4Sketch the output signal Y. State any assumption used.

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