The following circuit can compute a registered four-input XOR function. Each two-input XOR gate has a propagation delay of 100 ps and a contamination delay of 55 ps. Each flip-flop has a setup time of 60 ps, a hold time of 20 ps, a clock-to-Q maximum delay of 70 ps, and a clock-to-Q minimum delay of 50 ps.(1) If there is no clock skew, what is the maximum operating frequency of the circuit?(2) How much clock skew can the circuit tolerate if it must operate at 2 GHz?(3) How much clock skew can the circuit tolerate before it might experience a hold time violation?(4) (4.a) Redesign the combinational logic between the registers to be faster and tolerate more clockskew. Sketch the improved combinational circuit, which also uses three two-input XORs, and theregisters. (4.b) What is its maximum frequency if there is no clock skew? (4.c) How much clockskew can the circuit tolerate before it might experience a hold time violation? Exercise 3.9 The following circuit can compute a registered four-input XOR function. Each two-inputXOR gate has a propagation delay of 100 ps and a contamination delay of 55 ps. Each flip-flop has asetup time of 60 ps, a hold time of 20 ps, a clock-to-Q maximum delay of 70 ps, and a clock-to-Qminimum delay of 50 ps.(1) If there is no clock skew, what is the maximum operating frequency of the circuit?(2) How much clock skew can the circuit tolerate if it must operate at 2 GHz?(3) How much clock skew can the circuit tolerate before it might experience a hold time violation?(4) (4.a) Redesign the combinational logic between the registers to be faster and tolerate more clockskew. Sketch the improved combinational circuit, which also uses three two-input XORS, and theregisters. (4.b) What is its maximum frequency if there is no clock skew? (4.c) How much clockskew can the circuit tolerate before it might experience a hold time violation?CLKCLK

Answered: Exercise 3.9 The following circuit can…

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

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The following circuit can compute a registered four-input XOR function. Each two-input XOR gate has a propagation delay of 100 ps and a contamination delay of 55 ps. Each flip-flop has a setup time of 60 ps, a hold time of 20 ps, a clock-to-Q maximum delay of 70 ps, and a clock-to-Q minimum delay of 50 ps.
(1) If there is no clock skew, what is the maximum operating frequency of the circuit?
(2) How much clock skew can the circuit tolerate if it must operate at 2 GHz?
(3) How much clock skew can the circuit tolerate before it might experience a hold time violation?
(4) (4.a) Redesign the combinational logic between the registers to be faster and tolerate more clock
skew. Sketch the improved combinational circuit, which also uses three two-input XORs, and the
registers. (4.b) What is its maximum frequency if there is no clock skew? (4.c) How much clock
skew can the circuit tolerate before it might experience a hold time violation?

Exercise 3.9 The following circuit can compute a registered four-input XOR function. Each two-input
XOR gate has a propagation delay of 100 ps and a contamination delay of 55 ps. Each flip-flop has a
setup time of 60 ps, a hold time of 20 ps, a clock-to-Q maximum delay of 70 ps, and a clock-to-Q
minimum delay of 50 ps.
(1) If there is no clock skew, what is the maximum operating frequency of the circuit?
(2) How much clock skew can the circuit tolerate if it must operate at 2 GHz?
(3) How much clock skew can the circuit tolerate before it might experience a hold time violation?
(4) (4.a) Redesign the combinational logic between the registers to be faster and tolerate more clock
skew. Sketch the improved combinational circuit, which also uses three two-input XORS, and the
registers. (4.b) What is its maximum frequency if there is no clock skew? (4.c) How much clock
skew can the circuit tolerate before it might experience a hold time violation?
CLK
CLK

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