Example 9.7. In this example, we want to construct an 8-bit dedicated datapath for solving the following problem: Input an 8-bit number. Output a 1 if the number has the same number of 0’s and 1’s, otherwise, output a 0. (E.g., the number 10111011 will output a 0; whereas, the number 10100011 will output a 1.) he algorithm for solving the problem is shown in Figure 9.24. The WHILE loop is executed eight times using the counteight variable for the 8 bits in the input number n. For each bit in n, if it is a 1, the variable countbit is incremented, otherwise, it is decremented. At the end of the WHILE loop, if countbit is equal to 0, then there are the same number of 0’s and 1’s in n. After analyzing the algorithm, we conclude that the following registers and functional units are needed for the datapath: • An 8-bit shifter with parallel load register for storing and shifting n. • A 4-bit up counter for counteight. • A 4-bit up-down counter for countbit. • A “not equal to 8” comparator for looping eight times. • An “equal to 0” comparator for testing with countbit. The dedicated datapath for implementing the algorithm is shown in Figure 9.25. Notice that there are no connections between the shifter and the two counters; they are completely separate circuits. To extract bit 0 of n and test whether it is equal to a 1 or not, we only have to connect to the least significant bit, n0, of the shifter, and no active component is necessary. To test for (counteight ≠ 8), we use a 4-input NAND gate with the three least significant input bits inverted. When counteight is equal to eight, the NAND gate outputs a 0, which serves as the ending loop condition. Using the Down signal, the countbit register can be either incremented or decremented. Since register countbit is keeping track of the number of 0’s and 1’s, if it is a 0 at the end, it means that n has the same number of 0’s and 1’s. The NOR gate will output a 1 if countbit is a 0. Whether the output of the NOR gate actually is outputted will depend on whether the tri-state buffer is enabled or not. When the control unit asserts the Out signal to enable the tri-state buffer, this 1 signal also serves as the Done signal to inform the external user that the computation is completed. In other words, when the Done signal is asserted, the output value is the correct result for the computation. The control words for this example are shown in Figure 9.26. Notice that there are several control words with don’t-care values. For example, in control word 2 for initializing countbit to 0, it does not matter what the setting for the Down signal, is since we are not incrementing or decrementing the count.
Example 9.7.
In this example, we want to construct an 8-bit dedicated datapath for solving the following problem:
Input an 8-bit number. Output a 1 if the number has the same number of 0’s and 1’s, otherwise, output a 0. (E.g., the number 10111011 will output a 0; whereas, the number 10100011 will output a 1.)
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After analyzing the algorithm, we conclude that the following registers and functional units are needed for the datapath:
• An 8-bit shifter with parallel load register for storing and shifting n.
• A 4-bit up counter for counteight.
• A 4-bit up-down counter for countbit.
• A “not equal to 8” comparator for looping eight times.
• An “equal to 0” comparator for testing with countbit.
The dedicated datapath for implementing the algorithm is shown in Figure 9.25. Notice that there are no connections between the shifter and the two counters; they are completely separate circuits. To extract bit 0 of n and test whether it is equal to a 1 or not, we only have to connect to the least significant bit, n0, of the shifter, and no active component is necessary. To test for (counteight ≠ 8), we use a 4-input NAND gate with the three least significant input bits inverted. When counteight is equal to eight, the NAND gate outputs a 0, which serves as the ending loop condition. Using the Down signal, the countbit register can be either incremented or decremented. Since register countbit is keeping track of the number of 0’s and 1’s, if it is a 0 at the end, it means that n has the same number of 0’s and 1’s. The NOR gate will output a 1 if countbit is a 0. Whether the output of the NOR gate actually is outputted will depend on whether the tri-state buffer is enabled or not. When the control unit asserts the Out signal to enable the tri-state buffer, this 1 signal also serves as the Done signal to inform the external user that the computation is completed. In other words, when the Done signal is asserted, the output value is the correct result for the computation.
The control words for this example are shown in Figure 9.26. Notice that there are several control words with don’t-care values. For example, in control word 2 for initializing countbit to 0, it does not matter what the setting for the Down signal, is since we are not incrementing or decrementing the count.
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