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EXAMPLE 7.17 R₁ 68 ΚΩ R, < 20 ΚΩ G + VGS RD R$ ENGG CC ROT Determine ID VGS, and VDs for the p-channel JFET of Fig. 7.57. + '2.7 ΚΩ -o-20V OD + OS FIG. 7.57 Vps 1.8 ΚΩ IDSS = 8 mA Vp = 4 V Figure 2.13 Example for p-channel Voltage Divider Bias Circuit.

EXAMPLE 7.17 R₁ 68 ΚΩ R, < 20 ΚΩ G + VGS RD R$ ENGG CC ROT Determine ID VGS, and VDs for the p-channel JFET of Fig. 7.57. + '2.7 ΚΩ -o-20V OD + OS FIG. 7.57 Vps 1.8 ΚΩ IDSS = 8 mA Vp = 4 V Figure 2.13 Example for p-channel Voltage Divider Bias Circuit.

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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2.14 Example for p-channel JFET EXAMPLE 7.17 Determine ID, VGS, and Vps for the p-channel JFET of Fig. 7.57. R₁ 68 ΚΩ R, < 20 ΚΩ + VGS RD Rs ENGG CC POT + TID 2,7 ΚΩ OD + -20V FIG. 7.57 Vps 1.8 ΚΩ IDSS = 8 mA Vp = 4 V Figure 2.13 Example for p-channel Voltage Divider Bias Circuit.
Transcribed Image Text:2.14 Example for p-channel JFET EXAMPLE 7.17 Determine ID, VGS, and Vps for the p-channel JFET of Fig. 7.57. R₁ 68 ΚΩ R, < 20 ΚΩ + VGS RD Rs ENGG CC POT + TID 2,7 ΚΩ OD + -20V FIG. 7.57 Vps 1.8 ΚΩ IDSS = 8 mA Vp = 4 V Figure 2.13 Example for p-channel Voltage Divider Bias Circuit.
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