The timing stuff is still tricky to me. If I can get help going on the first one, I think I can figure out part b on my own. Thank you for your time and help. Pro XO Prio XA Intro XO Intro XO MTI XO Finc XCha XE Das XECE XO ECE X M You Xb Ans x +->A https://d2l.pdx.edu/d2l/le/content/876966/viewContent/5903059/ViewUpdate :T2 of 3+Automatic Zoom>>3. A timing diagram giving the S and R inputs for a NOR-gate S-R latch is shown below, andthe NOR-gate circuit is also shown for reference (QN = Q').a) Fill in the outputs Q and Q', starting with Q = 0 and Q' = 1. Assume the changeshappen instantaneously, i.e., ignore any propagation delays in the circuit.RQ-QNQ'b) Repeat the problem, but this time include propagation delays through the circuit.The propagation delay of each NOR gate is 10 ns, and each time division in the figure isalso 10 ns. Be careful, and include the different paths through the circuit!4:03 PMO Type here to search84%56°F11/30/20212

Given: Note : It is the kind notice that here student need only answer for first part a ,hence we are solving the same part a. In the above given question they have mentioned digital circuit which is having logic gates called nor gates. The mentioned digital circuit is a SR latch, SR latch is a sequential circuit whose output will depends upon present and past value of input. Latches are used to stor e 1 bit of information, latches are not supplied with the clock where flip-flops are clocked latches. Group of registers are known as flip flop, by the help of flip flop we can design counter circuit such as Johnson counter, ring counter, synchronous and asynchronous counters. For the given SR flip flop by writing the truth table of the standard SR latch we have written the waveform of the output.Truth table: S R Q Q' 0 0 HOLD HOLD 0 1 0(Reset) 1 1 0 1(Set) 0 1 1 0 ( Invalid) 0(Invalid) Explanation : Latches are not supplied by the clock. According to the SR latch truth table whenever the inputs of SR latch are ( S = 1 ,R = 0) the output was going to set. For the inputs of SR latch are ( S =0 ,R = 1) the output was going to reset. Whenever both the inputs of SR latch are logic low then the output is going to previous state. The major disadvantage of the SR latch is that whenever both the inputs are logic high then output is invalid output. Output Waveforms :