Hello. Please answer the attached Computer Organization/Design question and its parts correctly. The figure for Part D is attached in the next image. *If you answer the question and its parts correctly, I will give you a thumbs up. Thanks. *PCAddressPCSrcAddInstructionmemoryFigure For PART DIFADReadregister 1Readregister 2WriteregisterWritedataInstruction[31-0]Instruction[30, 14-12]RegWriteInstruction[11-7]Registers32ControlReaddata 1Readdata 2ImmGen64ID/EXWBMEXShiftleft 1↑AddSumALUcontrolALUSrcZeroALU ALUresultALUOPEX/MEMWBMBranchAddressWritedataMemWriteDatamemoryReaddataMemReadMEMWBWBMemtoRegMUXO Examine the difficulty of adding a proposed ss rs1, rs2, immed (Store Sum) instructionto RISC-V. Interpretation:Mem[Reg[rs 1]]= Reg[rs2] + immediatea. Which new functional blocks (if any) do we need for this instruction?b. Which existing functional blocks (if any) require modification?C. What new signals do we need (if any) from the control unit to support this instruction?d. Modify Figure bellow to demonstrate an implementation of this new instruction.* The figure for Part D is shown in the other attached photo.* Please solve each part correctly, and I will provide a Thumbs Up. Thank you.

Proposed ss rs1,rs2, immed (Store Sum) to RISC-VMem[Reg[rs1]]=Reg[rs2]+immediate And we need to write each question in the details explanation as per question requirement. (a) Which new functional blocks (if any) do we need for this instruction?EXPLANATIONWe do not need any new functional blocks to add the ss instruction to RISC-V. The ss instruction can be implemented using the existing ALU, registers, and memory system.(b) Which existing functional blocks (if any) require modification?EXPLANATIONThe ss instruction does not require any modification to the existing functional blocks. However, the control unit will need to be modified to generate the appropriate signals for the ss instruction.(c) What new signals do we need (if any) from the control unit to support this instruction?EXPLANATIONThe ss instruction requires the following new signals from the control unit:A signal to indicate that the ss instruction is being executed.A signal to select the register file to read from.A signal to select the register file to write to.A signal to indicate the immediate value to add to the register value.(d) Modify the figure below to demonstrate an implementation of this new instruction.The figure below shows the implementation of the ss instruction in RISC-V. The ss instruction is implemented using the existing ALU, registers, and memory system. The control unit generates the appropriate signals for the ss instruction, and the ALU performs the addition of the register value and the immediate value. The result of the addition is then stored in the memory location specified by the register address.EXPLANATIONThe ss instruction is a relatively simple instruction to implement, and it does not require any new functional blocks or significant modification to the existing functional blocks. The main challenge is to modify the control unit to generate the appropriate signals for the ss instructionConclusionThis question is that the ss guidance is generally basic guidance to execute in RISC-V. It requires no new useful blocks or critical adjustment to the current practical blocks. The primary test is to alter the control unit to produce the proper signs for the SS guidance.