Eight batch jobs arrive almost at the same time in the following order: II₁, II2, ..., II8.The table below contains their running times and priorities:JobП1 П2 П3 П4 П П П ПRunning time (in min) 14 11 20 10 8 18 7 9Priority 4 3 2 7 5 8 1 6The highest priority is 1.(a) Assume that the system has only one CPU core. Determine the order of executionof processes and the average turnaround time for the priority scheduling and thefirst-come, first-served algorithm.(b) Now assume that the system has 3 CPU cores. The following algorithm is used:whenever a CPU core is available (e.g., after a process terminates), the schedulerpicks a process with the highest priority from the queue. Determine the order ofexecution of processes and the average turnaround time. (For each process, you alsoneed to clearly indicate on which core it is executed.)(c) Now assume that the system has 2 CPU cores. The system may execute theprocesses in any order and arbitrarily distribute processes among cores. Find aschedule that minimises the largest turnaround time (i.e. the last process terminatesas soon as possible). Are there several such solutions? If yes, find the one that alsominimises the average turnaround time.

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Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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a. We are given a system with 2 levels of cache, L1 and L2. The CPU directly interfaces to the L1 cache, which has a hit time of 1 ns and a hit rate of 0.4. On misses, the L1 accesses the L2 cache, which has an access time of 20 ns, and a hit rate of 0.8. If the L2 misses, it accesses the main memory, which has an access time of 100 ns. Determine the average memory access time, of the CPU to the memory hierarchy.b. A cache is inserted between the main memory, which is 32 MB, and the CPU. This cache can accomodate 64 blocks and each block can accomodate 128 words (2B per word). How many possible blocks can be stored in one cache block if it is a direct-mapped cache?
Solve the given problems A and B
Given table consists of five processes with length of the CPU burst provided in milli seconds. Show all the calculations by applying Round-Robin scheduling algorithm with a time quantum of 4 milli seconds. Processes Burst Time (ms) 17 Pa 8 12 Pc 5 Pd 12 Pe a) Draw a Gantt chart to show round-robin scheduling. b) Calculate the waiting time for each process. c) Calculate the average waiting time.
Systolic arrays are what MISD machines are. "Wavefronts" or pipeline networks of data processing pieces are what systolic arrays are referred to as. Since data triggers the beginning of the execution process, these components are self-contained and do not need programme counters. To ensure that calculations are performed in "lock-step," the compute and communication phases in systolic arrays with synchronised clocks are switched by each CPU.
Solve Both Problem A and B. Use the information from A to solve B
A computer system contains a big endian byte addressable memory system with 8 separate memory modules. Each memory module is 32 bits wide and contains 134217728 cells. Cells within each memory module are numbered 0 through 134217727. a) If the memory employs high order interleaving, what is the 32-bit memory address of cell 1048578 within module 3? b) If the high order interleaved memory uses little-endian instead of big-endian storage order, what is the 32-bit memory address of cell 511 within module 1? c) If the memory employs low order interleaving, what is the 32-bit memory address of byte 1048575 within module 2? Bytes are numbered starting from 0. Express the address in hex. d) What is the main advantage of using low-order interleaved memory compared to using high-order interleaved memory?
We have two jobs X and Y. The combination of them is called job Z. Thus Z= (Note the order in the sequence.) Job X is 3s CPU followed by 3s I/O. Y is 3s I/O followed by 3s CPU. (A). Serial Execution. (A1) What is the turnaround time of Z? Tr(Z) = [Select] (A2) What is the cpu utilization? CPU(Z) = [Select] (B). Batch Multiprogramming. (B1) What is the turnaround time of Z? Tr(Z) = [Select] (B2) What is the CPU utilization ? CPU(Z) = [Select] (C) Time sharing with timeslice 1s. (C1) What is the turnaround time of Z? Tr(Z) = [Select] (C2) What is the CPU utilization ? CPU(Z)=[Select]
8 A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a maximum of 106 instructions per second. An average instruction requires five ma- chine cycles, three of which use the memory bus. A memory read or write operation uses one machine cycle. Suppose that the processor is continuously executing "background" programs that require 95% of its instruction execution rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is to be used to transfer very large blocks of data between M and D. a. If programmed I/O is used and each one-word I/O transfer requires the processor to execute two instructions, estimate the maximum I/O data-transfer rate, in words per second, possible through D. b. Estimate the same rate if DMA is used.
3. Consider the following table. Process Arrival time Priority CPU I/O СPU P1 2 10 20 P2 4 1 15 10 P3 6 3 10 5 Draw the Gantt chart of CPU and I/O if, b) CPU is scheduled by RR with quantum=5ms and I/O scheduling is by preemptive-priority. Priority is highest at level 3 and lowest at level 1.
Assume every process requires 3 milli seconds of service time in a system with single processor. If new processes are arriving at the rate of 100 processes per minute, then estimate the fraction of time CPU is busy in system?
Assume that a system is using write-though cache. It has 70% write hits. The cache operates in look-aside mode with a read-hit ratio of 80%. The program run on the system is such that it has memory reference for read 70% of time and for write is 30%. The main memory cycle time is 100ns and the cache access is 20ns.(Further assume we are using no write allocate policy) Difference between average write access time and average read access time is (in ns).
8 A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a maximum of 106 instructions per second. An average instruction requires five ma- chine cycles, three of which use the memory bus. A memory read or write operation uses one machine cycle. Suppose that the processor is continuously executing "background" programs that require 95% of its instruction execution rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is to be used to transfer very large blocks of data between M and D. a. If programmed I/O is used and each one-word I/O transfer requires the processor to execute two instructions, estimate the maximum I/O data-transfer rate, in words per second, possible through D. b. Estimate the same rate if DMA is used.

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