e) Let us consider a memory hierarchy (main memory + cache) given by: a. Memory size 1 Giga words of 16 bit (word addressed) Cache size 1 Mega words of 16 bit (word addressed) c. Cache block size 256 words of 16 bit b. d. Let us consider the following cache structures: i. direct mapped cache; ii. fully associative cache; iii. 2-way set-associative cache; iv. 4-way set-associative cache; v. 8-way set-associative cache. a) Calculate the structure of the addresses for the previous cache structures; b) Calculate the number of blocks for the previous cache structures; c) Calculate the number of sets for the previous set associative caches.

e) Let us consider a memory hierarchy (main memory + cache) given by: a. Memory size 1 Giga words of 16 bit (word addressed) Cache size 1 Mega words of 16 bit (word addressed) c. Cache block size 256 words of 16 bit b. d. Let us consider the following cache structures: i. direct mapped cache; ii. fully associative cache; iii. 2-way set-associative cache; iv. 4-way set-associative cache; v. 8-way set-associative cache. a) Calculate the structure of the addresses for the previous cache structures; b) Calculate the number of blocks for the previous cache structures; c) Calculate the number of sets for the previous set associative caches.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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3. Assuming a cache of 4096 blocks, a four-word block size, each word contains 4 bytes, and a 64-bits memory address. Memory is byte addressable, and random block replacement policy and write back policy are implemented. Find the total number of tag bits for caches that are a) direct-mapped b) 2-way set associative c) 4-way set associative d) Fully associative
Consider a 2-way set associative cache (S,E,B,m) = (8,2,4,13) Excluding the overhead of the tags and valid bits, what is the capacity of this cache? Draw a figure of this cache. Draw a diagram that shows the parts of the address that are used to determine the cache tag, cache set index, and cache block offset.
4. Find all instructors in Finance department who have taught some course in 2008. 5. Find all students from Physics department who took course 'CS-319'.
CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.
A byte offset of 2 in an address means that each set in a multiway set associative (or in the directly mapped) cache has 4 bytes per set, per cache line. Keeping this in mind, answer the questions given the following details. A cache is organized as a 4 way set associative cache Each set's cache line consists of 4 words (meaning there are 16 bytes per line, for each set of the cache). Each set individually has one Valid bit, and one Dirty bit, for each line. The tag field of this cache is 8 bits wide. The address is 32 bits wide. Question 1g) If we have a write through cache coherency policy, will either of the above organizations make a difference in the amount of power used to do one write through operation (specifically above this cache layer, in the upper level memory structures to maintain coherency.
1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.
Assume a cache of 1 MB organized as 32 bytes each line. The main memory is 256 MB. a. Determine the number of blocks in main memory b. Determine how to split the address (s-r, r, w) for direct mapping. c. Determine how to split the address (s, w) for associative mapping. d. Determine how to split the address (s-d, d, w) for set-associative each cache set is 4 lines of the cache.
Question 4 Given a computer with a memory system having a30_bit address, a cache consisting of 1024 blocks each is 8 words. For the following cache types: Direct Mapped (DM), Fully_ associative (FA), Two_way set associative (2_way), Four_way set associative (4_way), Eight_way set associative (8_way), calculate the following values as specified. (Use paper and pencil to do needed calculations and write only the final answer in the given blank space). 1) 4_way: The size of the index field =Blank 1bits 2) 8_way: The size of the index field =Blank 2bits 3) DM: The size of the index field = Blank 3bits 4) 2_way: The size of the index field =Blank 4bits 5) The size of the offset field = Blank 5bits 6) 4_way: The size of the tag field =Blank 6bits 7) 8_way: The size of the tag field =Blank 7bits 8) DM: The size of the tag field =Blank 8bits 9) 2_way: The size of the tag field =Blank 9bits 10) FA: The size of the tag field =Blank 10bits
1. Suppose we have a 32KB direct-mapped data cache with 32-byteblocks.a) Show how a 32-bit memory address is divided into tag, index andoffset. Show clearly how many bits are in each field.b) How many total bits are there in this cache?