Draw the logic circuits that can achieve the following truth tables: A B C Output A B C Output 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1
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- NEED ONLY NEAT HANDWRITTEN SOLUTION .ANSWER ALLAnswer the D, E and F partPerform the addition of the following 8-bit 2's complement numbers using 2's complement arithmetic. (Reminder: 2's complement numbers are signed numbers.) a) 11001001 + 00110011 b) 10011011 + 01101111 c) 01011010 + 10110110 d) 11001000 + 11100101 Convert each result from the previous problem to signed decimal. Draw the block diagram of the circuit required to implement the operation in Problem 3.
- What parity bit, P, should be added to the following data if the parity is EVEN? If the parity is ODD? a. 1111100 b. 1010110 c. 0001101Subtract the following 16-bit binary numbers. a. 11001011 00101000. - 10011110 01011011, b. 10111100 10111000, - 10011000 11110011223. The binary number 101110101111010 can be written in octal as a. 515628 b. 565778 c. 656278 d. 565728
- Using the analysis technique where you first extract the truth table and then use it to derive the output’s logic expression, analyze the circuit. Record your results below. I added the circuit as an image Conclusion In your own words, describe the process used to analyze a logic circuit where you first extract a truth table and then derive the logic expression. 2.Again, in your own words, describe the process used to analyze a logic circuit where you first extract the logic expression and then derive the truth table.7. Read the following table, and design a logic circuit that can convert the binary code from BCD8421 to 2421. Decimal Digit BCD 8421 2421 0000 0000 1 0001 0001 2 0010 0010 3 0011 0011 4 0100 0100 5 0101 1011 0110 1100 7 0111 1101 1000 1001 8 1110 9 1111 1010 0101 Unused 1011 0110 bit 1100 0111 combi- 1101 1000 nations 1110 1001 1111 1010 Fig 1Design the following combinational logic circuit with a four-bit input and a three-bit output. The input represents two unsigned 2-bit numbers: A1 A0 and B1 B0. The output C2 C1.C0 is the result of the integer binary division A1 A0/B1 B0 rounded down to three bits. The 3-bit output has a 2-bit unsigned whole part C2 C1 and a fraction part CO. The weight of the fraction bit CO is 21. Note the quotient should be rounded down, i.e. the division 01/11 should give the outputs 00.0 (1/3 rounded down to 0) not 00.1 (1/3 rounded up to 0.5). A result of infinity should be represented as 11.1. A minimal logic implementation is not required. (Hint: start by producing a truth table of your design).
- a) For the given logic circuit diagram write the program by using the gate level modeling. b) For the given truth table write the program by using the data flow Modelling. c) Write the test bench of the given logic circuit with all possibilities Y1 Y2 Y3 Y4 Y5 Y6 Y7 A2 A1 A0Exercises : Convert the following binary numbers to Hexadecimal numbers: (b) 1100111010002 (a)11001010010101112 (c) 101010. 101012 (d) 1111110001.011010012 0110111012 (e) 1011001110. Answers:Answer n,o,p