Data communıcatıon digital data is transmitted via analog ASK and PSK are used together to increase the number of bits transmitted a)For m=8,suggest a solution and define signal elements , and then draw signals for the following sent data data = 0 1 0 1 1 0 0 0 1 0 1 1
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Data communıcatıon digital data is transmitted via analog ASK and PSK are used together to increase the number of bits transmitted
a)For m=8,suggest a solution and define signal elements , and then draw signals for the following sent data
data = 0 1 0 1 1 0 0 0 1 0 1 1
Step by step
Solved in 2 steps with 3 images
- Digital communicationA 4-bit carry-look ahead adder (CLA) is used to add the two numbers: A(A3A2A1A0) = 0110 and B (B3B2B1B0) = 1001 with an external carry-in C0=1. Use the CLA carry-out equation ( Si = Pi Ci , Ci + 1 = Gi + Pi Ci Where Pi = Ai Bi and Gi = AiBi) to compute the values of following outputs?I. Carry-Out = C3II. Sum = S3Communication
- An 9-bit binary number is used to represent an analog value in the rangefrom -10oC to 100oC, determine the resolution of the system andinterprete your result.RCA: Ripple Carry Adder Example: given the time for the signal to pass through a half adder is (0.3 μS) and for the Full Adder is (0.32 μS), calculate the time required to provide the results for a 32- bit RCA?A B C 3 Cost Σ Σ Σ, A B C 3 Cout FIGURE 6-78 Σ Search Σ A B C 595 Cout 2 2₁ Under 6. The input waveforms in Figure 6-78 are applied to a 2-bit adder. Determine the waveforms for the sum and the output carry in relation to the inputs by constructing a timing diagram. mesta. A₁ A₂ B₁ B, A B Cin Cin Cout M 75 A B Cin 14 Σ₁ 7 1 HE
- 8. Consider transmitting a digital data: 10111000101. Draw the signal representation when a. Using the Manchester method b. Using the differential Manchester method c. Using the Bipolar methoda) A multiplexer (MUX) is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. Design a 8:1 multiplexer using the function: F(A,B,C,D)= (0,2,4,5,7,10,12,14,15), Major Topic Multiplexers b) Implement the Boolean function below using a 4:1 multiplexer F(A, B,C)=Em (0, 2, 5, 6) Major Topic Multiplexers Text Blooms Designation AP Major Topic Demultiplexers Blooms Designation AN c) A Demultiplexer (Demux) has one input, 2n possible outputs and n control or selection lines. It is also called a data distributor. Design 8:1 Demultiplexer for a mobile telecom company Blooms Designation AP d) Draw the Set-Reset (SR) Latch using NAND gates. Explain its operations Major Topic Memories Devices Blooms Designation AN4 bit 2’s Complement Multiplier INPUT A: 4 bit 2’s Complement number INPUT B: 4 bit 2’s Complement number OUTPUT: the product of A x B represented as a 8 bit 2’s Complement number PART 3: Build a 4 Bit UNSIGNED Multiplier as a subcircuit named UnsignedMultiplier use AND gate ,full and half adders for the circuit
- 4 bit 2’s Complement Multiplier INPUT A: 4 bit 2’s Complement numberINPUT B: 4 bit 2’s Complement numberOUTPUT: the product of A x B represented as a 8 bit 2’s Complement number Do this:Build a 4 Bit UNSIGNED Multiplier as a subcircuit named UnsignedMultiplier use AND gate ,full and half adders for the circuitThe Excess-3 coding system is a four-bit digital coding system for encoding all decimal digits from 0 to 9. To encode a decimal digit, we add three to it and then convert the result to binary. A valid code has the following range:1. Minimum = 0011, encoding decimal 0( 0 + 3 = 3 = 0011)2. Maximum = 1100, encoding decimal 9(9 + 3 =12 = 1100)Design a logic circuit that will detect an error if a four-bit number is not a valid Excess-3 number. (Hint: Use four input variables to represent the four bits of the Excess_3 number. If the combination of the input bits is 0000,0001,0010,1101,1110, or 1111, the output will be HIGH. For all other cases, the output will be LOW.)Design a 2-bit binary full-adder circuit using a true-output decoder. Assume carry input of the 2-bit binary full-adder is zero. Circuit adds two 2-bit binary numbers A, consisting of bits A1, AO, and B, consisting of bits B1, BO. The sum that is produced by the adder circuit consists of two sum bits S1, SO and a carry out bit CO. Provide:i. Boolean equations for S1, SO and Co.ii. Completely labelled logic diagram of decoder that implements the required operation. (You can represent the decoder in form of block diagram)