DATA AND RESULTS State Table 9-1: NAND NOR implementation implementation next next output Input R output Q(t+1) output Q(t+1) 1. 1 1 1 1 1 1 1 State table 9-2: Q(t+1) 1 State table 9-3: JK flip-flop next output: Q(t+1) output input 1 11

Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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Question

Construct the RS latch (NAND and NOR implementation). Connect the inputs and
outputs properly to the digital trainer. Don’t forget to connect the DC supply.
Complete the state stable 9-1.
2. Construct the D latch (NAND implementation). Connect the inputs and outputs
properly to the digital trainer. Don’t forget to connect the DC supply. Complete the
state table 9-2.
3. Connect the inputs and outputs properly to the digital trainer. Don’t forget to connect
the DC supply. Complete the state table 9-3.

DATA AND RESULTS
State Table 9-1:
NAND
implementation implementation
NOR
next
output
O(t+1)
next
output
Input
output
R
Q(t+1)
1
1
1
1
1
1
1
1
1
State table 9-2:
D
Q(t+1)
1
1
State table 9-3:
JK flip-flop
next
output
O(t+1)
output
input
오
0|0
1
1
1.
1
1
1
ooo o o-
ooooo
Transcribed Image Text:DATA AND RESULTS State Table 9-1: NAND implementation implementation NOR next output O(t+1) next output Input output R Q(t+1) 1 1 1 1 1 1 1 1 1 State table 9-2: D Q(t+1) 1 1 State table 9-3: JK flip-flop next output O(t+1) output input 오 0|0 1 1 1. 1 1 1 ooo o o- ooooo
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