D En D | Next state of Q En 0 X No change 1 0Q= 0; reset state 1 1Q= 1; set state %3D (a) Logic diagram (b) Function table

Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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The D latch of Fig. 5.6 is constructed with four NAND gates and an inverter. Consider the following three other ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation. Use NOR gates for the SR latch part and AND gates for the other two. An inverter may be needed.

D
En D | Next state of Q
En
0 X No change
1 0Q= 0; reset state
1 1Q= 1; set state
%3D
(a) Logic diagram
(b) Function table
Transcribed Image Text:D En D | Next state of Q En 0 X No change 1 0Q= 0; reset state 1 1Q= 1; set state %3D (a) Logic diagram (b) Function table
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Function table-

En                       D                                        Next State of Q

0                        x                                          No change

1                        0                                          0;   Reset state

1                        1                                         1 ;    Set state

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

          

          

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