O 2.5 V 1.81 2.5 V Q +2.5 V 2.5 V Q2.5 V 1.68 (1.56 +4 VO 3.72 3.81 ML. ML. 4 (4) 28.8 kQ >L= 2880 1.28 4.71 471 꼭꾸 Ms 꾸 미어 мо Ms 꼭꾸 (a) (b) (c) (d) (e) Figure 6.24 Comparison of various NMOS inverter designs: (a) Inverter with resistor load, (b) saturated load inverter,

Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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Draw the schematic for a four-input NOR gate with
a saturated load device. What are the W/L ratios of
all the transistors, based on the reference inverter ? (b) What is VL if all the logic inputs are equal to 1?

O 2.5 V
1.81
2.5 V
Q +2.5 V
2.5 V
Q2.5 V
1.68 (1.56
+4 VO
3.72 3.81
ML.
ML.
4 (4)
28.8 kQ >L= 2880
1.28
4.71
471
꼭꾸
Ms 꾸 미어
мо
Ms
꼭꾸
(a)
(b)
(c)
(d)
(e)
Figure 6.24 Comparison of various NMOS inverter designs: (a) Inverter with resistor load, (b) saturated load inverter,
Transcribed Image Text:O 2.5 V 1.81 2.5 V Q +2.5 V 2.5 V Q2.5 V 1.68 (1.56 +4 VO 3.72 3.81 ML. ML. 4 (4) 28.8 kQ >L= 2880 1.28 4.71 471 꼭꾸 Ms 꾸 미어 мо Ms 꼭꾸 (a) (b) (c) (d) (e) Figure 6.24 Comparison of various NMOS inverter designs: (a) Inverter with resistor load, (b) saturated load inverter,
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