CSE 224 Project Part 2 1. Design VSCPU with interrupt handling Design VSCPU with interrupt handling and all instructions. Instruction set of VSCPU can be found in lab 5 doc README.md file. You can use Add only VSCPU design as an example which can be found in YULEARN. You can check lab 6 for state machine design of VSCPU with interrupt handling. Your design module name, inputs and outputs should be named like below. Designs which are not following this get 0 from this part. module VerySimpleCPU(clk, rst, data_fromRAM, wrEn, addr_toRAM, data_toRAM, interrupt); input clk, rst; input wire [31:0] data_fromRAM; input interrupt; output reg wrEn; output reg[SIZE-1:0] addr_toRAM; output reg[31:0] data_toRAM;
CSE 224 Project Part 2 1. Design VSCPU with interrupt handling Design VSCPU with interrupt handling and all instructions. Instruction set of VSCPU can be found in lab 5 doc README.md file. You can use Add only VSCPU design as an example which can be found in YULEARN. You can check lab 6 for state machine design of VSCPU with interrupt handling. Your design module name, inputs and outputs should be named like below. Designs which are not following this get 0 from this part. module VerySimpleCPU(clk, rst, data_fromRAM, wrEn, addr_toRAM, data_toRAM, interrupt); input clk, rst; input wire [31:0] data_fromRAM; input interrupt; output reg wrEn; output reg[SIZE-1:0] addr_toRAM; output reg[31:0] data_toRAM;
Computer Networking: A Top-Down Approach (7th Edition)
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ISBN:9780133594140
Author:James Kurose, Keith Ross
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![CSE 224 Project Part 2
1. Design VSCPU with interrupt handling
Design VSCPU with interrupt handling and all instructions. Instruction set of VSCPU can be
found in lab 5 doc README.md file. You can use Add only VSCPU design as an example which
can be found in YULEARN. You can check lab 6 for state machine design of VSCPU with
interrupt handling.
Your design module name, inputs and outputs should be named like below. Designs which are
not following this get 0 from this part.
module VerySimpleCPU(clk, rst, data_fromRAM, wrEn, addr_toRAM, data_toRAM,
Interrupt);
input clk, rst;
input wire [31:0] data_fromRAM;
input interrupt;
output reg wrEn3;
output reg[SIZE-1:0] addr_toRAM;
output reg[31:0] data_toRAM;](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Ffa52d2d2-d207-4a46-950f-a53db3f2d2ca%2Fa01d01c4-27d5-4ee5-9615-e9efdac4e677%2F0obudx8_processed.jpeg&w=3840&q=75)
Transcribed Image Text:CSE 224 Project Part 2
1. Design VSCPU with interrupt handling
Design VSCPU with interrupt handling and all instructions. Instruction set of VSCPU can be
found in lab 5 doc README.md file. You can use Add only VSCPU design as an example which
can be found in YULEARN. You can check lab 6 for state machine design of VSCPU with
interrupt handling.
Your design module name, inputs and outputs should be named like below. Designs which are
not following this get 0 from this part.
module VerySimpleCPU(clk, rst, data_fromRAM, wrEn, addr_toRAM, data_toRAM,
Interrupt);
input clk, rst;
input wire [31:0] data_fromRAM;
input interrupt;
output reg wrEn3;
output reg[SIZE-1:0] addr_toRAM;
output reg[31:0] data_toRAM;
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