CP4.8 A negative feedback control system is depicted in Figure CP4.8. Suppose that our design objective is to find a controller G.(s) of minimal complexity such that our closed-loop system can track a unit step input with a steady-state error of zero. (a) As a first try, consider a simple proportional controller G,(s) = K, %3D
CP4.8 A negative feedback control system is depicted in Figure CP4.8. Suppose that our design objective is to find a controller G.(s) of minimal complexity such that our closed-loop system can track a unit step input with a steady-state error of zero. (a) As a first try, consider a simple proportional controller G,(s) = K, %3D
Introductory Circuit Analysis (13th Edition)
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![CP4.8 A negative feedback control system is depicted in
Figure CP4.8. Suppose that our design objective is to
find a controller G.(s) of minimal complexity such
that our closed-loop system can track a unit step input
with a steady-state error of zero.
(a) As a first try, consider a simple proportional
controller
G,(s) = K,
%3D
where K is a fixed gain. Let K = 2. Plot the unit
step response and determine the steady-state
error from the plot.
(b) Now consider a more complex controller
K,
G.(s) = K, +
%3D
= 2 and K1 = 20. This controller is
where Ko
known as a proportional, integral (PI) controller.
Plot the unit step response, and determine the
steady-state error from the plot.
(c) Compare the results from parts (a) and (b), and
discuss the trade-off between controller complex-
ity and steady-state tracking error performance.
Process
Controller
10
s+ 10
Y(s)
R(s)
G(s)](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Ff323ee9d-7d94-4ef6-846e-2bdf97f2c11f%2F7c1cc531-aea4-441f-9bc8-5d34e5fd7cb8%2F1dlkwu9_processed.jpeg&w=3840&q=75)
Transcribed Image Text:CP4.8 A negative feedback control system is depicted in
Figure CP4.8. Suppose that our design objective is to
find a controller G.(s) of minimal complexity such
that our closed-loop system can track a unit step input
with a steady-state error of zero.
(a) As a first try, consider a simple proportional
controller
G,(s) = K,
%3D
where K is a fixed gain. Let K = 2. Plot the unit
step response and determine the steady-state
error from the plot.
(b) Now consider a more complex controller
K,
G.(s) = K, +
%3D
= 2 and K1 = 20. This controller is
where Ko
known as a proportional, integral (PI) controller.
Plot the unit step response, and determine the
steady-state error from the plot.
(c) Compare the results from parts (a) and (b), and
discuss the trade-off between controller complex-
ity and steady-state tracking error performance.
Process
Controller
10
s+ 10
Y(s)
R(s)
G(s)
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