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Consider the following assembly code: Description Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R2 Add contents of RI and R5 and store to R7 Instruction LD RI, 45(R2) ADD R7, RI, RS Subtract content of R7 from content of R1 and save to R8 Logical Ex-OR between contents of R8 & R8. Store result to R7 Jump to Target if R7 is Zero SUB R8, RI, R7 XOR R7, R8, R8 BEZ R7, Target Read data from memory and store in R5. Memory address is calculated by adding 50 to the content of R2 Read data from memory and store in R8. Memory address is calculated by adding 45 to the content of R2 Add contents of R8 and R5 and store to RIO Logical AND between contents of R3 & R4. Store result to R2 Add contents of R2 and R8 and store to R10 LD R5, 50(R2) LD R8, 45(R2) ADD R10, R8, R5 Target: AND R2, R3, R4 ADD R10, R8, R2 END a) Identify each type of data dependency; list the two instructions involved; identify which instruction is dependent b) Use five-stage pipeline containing fetch, decode, memory read, execute, write-back units, show the execution of above instructions. Data dependencies and control hazards, if detected must be resolved by stalling the pipeline as required. Assume that a multi-port RAM is used with the CPU running at 1GHZ. Calculate the execution time and compare time that would have required in a non-pipelined processor to run the same program.

Consider the following assembly code: Description Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R2 Add contents of RI and R5 and store to R7 Instruction LD RI, 45(R2) ADD R7, RI, RS Subtract content of R7 from content of R1 and save to R8 Logical Ex-OR between contents of R8 & R8. Store result to R7 Jump to Target if R7 is Zero SUB R8, RI, R7 XOR R7, R8, R8 BEZ R7, Target Read data from memory and store in R5. Memory address is calculated by adding 50 to the content of R2 Read data from memory and store in R8. Memory address is calculated by adding 45 to the content of R2 Add contents of R8 and R5 and store to RIO Logical AND between contents of R3 & R4. Store result to R2 Add contents of R2 and R8 and store to R10 LD R5, 50(R2) LD R8, 45(R2) ADD R10, R8, R5 Target: AND R2, R3, R4 ADD R10, R8, R2 END a) Identify each type of data dependency; list the two instructions involved; identify which instruction is dependent b) Use five-stage pipeline containing fetch, decode, memory read, execute, write-back units, show the execution of above instructions. Data dependencies and control hazards, if detected must be resolved by stalling the pipeline as required. Assume that a multi-port RAM is used with the CPU running at 1GHZ. Calculate the execution time and compare time that would have required in a non-pipelined processor to run the same program.

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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4. Consider the following assembly code: Instruction Description LD RI, 45(R2) Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R2 ADD R7, RI, RS Add contents of R1 and R5 and store to R7 SUB R8, R1, R7 Subtract content of R7 from content of R1 and save to R8 Logical Ex-OR between contents of R8 & R8. Store result to R7 Jump to Target if R7 is Zero XOR R7, R8, R8 BEZ R7, Target LD R5, 50(R2) Read data from memory and store in R5. Memory address is calculated by adding 50 to the content of R2 LD R8, 45(R2) Read data from memory and store in R8. Memory address is calculated by adding 45 to the content of R2 ADD R10, R8, R5 Add contents of R8 and R5 and store to R10 Logical AND between contents of R3 & R4. Store result to R2 Add contents of R2 and R8 and store to R10 Target: AND R2, R3, R4 ADD R10, R8, R2 END a) Identify each type of data dependency; list the two instructions involved; identify which instruction is dependent b) Use five-stage pipeline containing fetch, decode, memory read, execute, write-back units, show the execution of above instructions. Data dependencies and control hazards, if detected must be resolved by stalling the pipeline as required. Assume that a multi-port RAM is used with the CPU running at IGHZ. Calculate the execution time and compare time that would have required in a non-pipelined processor to run the same program.
Transcribed Image Text:4. Consider the following assembly code: Instruction Description LD RI, 45(R2) Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R2 ADD R7, RI, RS Add contents of R1 and R5 and store to R7 SUB R8, R1, R7 Subtract content of R7 from content of R1 and save to R8 Logical Ex-OR between contents of R8 & R8. Store result to R7 Jump to Target if R7 is Zero XOR R7, R8, R8 BEZ R7, Target LD R5, 50(R2) Read data from memory and store in R5. Memory address is calculated by adding 50 to the content of R2 LD R8, 45(R2) Read data from memory and store in R8. Memory address is calculated by adding 45 to the content of R2 ADD R10, R8, R5 Add contents of R8 and R5 and store to R10 Logical AND between contents of R3 & R4. Store result to R2 Add contents of R2 and R8 and store to R10 Target: AND R2, R3, R4 ADD R10, R8, R2 END a) Identify each type of data dependency; list the two instructions involved; identify which instruction is dependent b) Use five-stage pipeline containing fetch, decode, memory read, execute, write-back units, show the execution of above instructions. Data dependencies and control hazards, if detected must be resolved by stalling the pipeline as required. Assume that a multi-port RAM is used with the CPU running at IGHZ. Calculate the execution time and compare time that would have required in a non-pipelined processor to run the same program.
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