Consider a simple in-order processor with the following characteristics: Consists of a pipeline where one instruction is issued each cycle if possible. • An instruction can issue once all of its dependencies are satisfied. • There is no limit to the number of functional units. • Do not assume all operands are read prior to any being written in a given cycle. Given the following sequential list of instructions and instruction latencies: A. 1dw $r5 = 12[$r8] B. stw 8[$r2] = $r7 c. 1dw $r2 = 4[$r4] D. stw 12[$r8] = $r2 Instruction Latency add sub 1dw stw mpy 2 2 5 7 1. What is the CPI for sequential execution of the code with no data speculation? 2. Create a new schedule to maximize instruction level parallelism (ILP) using instruction scheduling and data speculation, but without register renaming. o Please maintain the original ordering of the instructions. Make sure you include appropriate latencies in the provided schedule. o Calculate the new CPI, assuming no data speculation overhead and that the two locations did not collide
Consider a simple in-order processor with the following characteristics: Consists of a pipeline where one instruction is issued each cycle if possible. • An instruction can issue once all of its dependencies are satisfied. • There is no limit to the number of functional units. • Do not assume all operands are read prior to any being written in a given cycle. Given the following sequential list of instructions and instruction latencies: A. 1dw $r5 = 12[$r8] B. stw 8[$r2] = $r7 c. 1dw $r2 = 4[$r4] D. stw 12[$r8] = $r2 Instruction Latency add sub 1dw stw mpy 2 2 5 7 1. What is the CPI for sequential execution of the code with no data speculation? 2. Create a new schedule to maximize instruction level parallelism (ILP) using instruction scheduling and data speculation, but without register renaming. o Please maintain the original ordering of the instructions. Make sure you include appropriate latencies in the provided schedule. o Calculate the new CPI, assuming no data speculation overhead and that the two locations did not collide
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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![Consider a simple in-order processor with the following characteristics:
• Consists of a pipeline where one instruction is issued each cycle if possible.
• An instruction can issue once all of its dependencies are satisfied.
• There is no limit to the number of functional units.
• Do not assume all operands are read prior to any being written in a given cycle.
Given the following sequential list of instructions and instruction latencies:
A. 1dw $r5 = 12[$r8]
B. stw 8[$r2] = $r7
c. 1dw $r2 = 4[$r4]
D. stw 12[$r8] = $r2
Instruction Latency
add
sub
1dw
stw
mpy
2
2
5
7
4
1. What is the CPI for sequential execution of the code with no data speculation?
2. Create a new schedule to maximize instruction level parallelism (ILP) using instruction scheduling and data speculation, but without
register renaming.
o Please maintain the original ordering of the instructions. Make sure you include appropriate latencies in the provided schedule.
o Calculate the new CPI, assuming no data speculation overhead and that the two locations did not collide](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F1fc05a39-034c-4d72-a4a1-ee451099dd5e%2F92951bc4-cacf-4d92-b40d-91ddb1021331%2Fwxwwuuf_processed.png&w=3840&q=75)
Transcribed Image Text:Consider a simple in-order processor with the following characteristics:
• Consists of a pipeline where one instruction is issued each cycle if possible.
• An instruction can issue once all of its dependencies are satisfied.
• There is no limit to the number of functional units.
• Do not assume all operands are read prior to any being written in a given cycle.
Given the following sequential list of instructions and instruction latencies:
A. 1dw $r5 = 12[$r8]
B. stw 8[$r2] = $r7
c. 1dw $r2 = 4[$r4]
D. stw 12[$r8] = $r2
Instruction Latency
add
sub
1dw
stw
mpy
2
2
5
7
4
1. What is the CPI for sequential execution of the code with no data speculation?
2. Create a new schedule to maximize instruction level parallelism (ILP) using instruction scheduling and data speculation, but without
register renaming.
o Please maintain the original ordering of the instructions. Make sure you include appropriate latencies in the provided schedule.
o Calculate the new CPI, assuming no data speculation overhead and that the two locations did not collide
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