Consider a simple in-order processor with the following characteristics: Consists of a pipeline where one instruction is issued each cycle if possible. • An instruction can issue once all of its dependencies are satisfied. • There is no limit to the number of functional units. • Do not assume all operands are read prior to any being written in a given cycle. Given the following sequential list of instructions and instruction latencies: A. 1dw $r5 = 12[$r8] B. stw 8[$r2] = $r7 c. 1dw $r2 = 4[$r4] D. stw 12[$r8] = $r2 Instruction Latency add sub 1dw stw mpy 2 2 5 7 1. What is the CPI for sequential execution of the code with no data speculation? 2. Create a new schedule to maximize instruction level parallelism (ILP) using instruction scheduling and data speculation, but without register renaming. o Please maintain the original ordering of the instructions. Make sure you include appropriate latencies in the provided schedule. o Calculate the new CPI, assuming no data speculation overhead and that the two locations did not collide

Consider a simple in-order processor with the following characteristics: Consists of a pipeline where one instruction is issued each cycle if possible. • An instruction can issue once all of its dependencies are satisfied. • There is no limit to the number of functional units. • Do not assume all operands are read prior to any being written in a given cycle. Given the following sequential list of instructions and instruction latencies: A. 1dw $r5 = 12[$r8] B. stw 8[$r2] = $r7 c. 1dw $r2 = 4[$r4] D. stw 12[$r8] = $r2 Instruction Latency add sub 1dw stw mpy 2 2 5 7 1. What is the CPI for sequential execution of the code with no data speculation? 2. Create a new schedule to maximize instruction level parallelism (ILP) using instruction scheduling and data speculation, but without register renaming. o Please maintain the original ordering of the instructions. Make sure you include appropriate latencies in the provided schedule. o Calculate the new CPI, assuming no data speculation overhead and that the two locations did not collide

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Question

Consider a simple in-order processor with the following characteristics:
• Consists of a pipeline where one instruction is issued each cycle if possible.
• An instruction can issue once all of its dependencies are satisfied.
• There is no limit to the number of functional units.
• Do not assume all operands are read prior to any being written in a given cycle.
Given the following sequential list of instructions and instruction latencies:
A. 1dw $r5 = 12[$r8]
B. stw 8[$r2] = $r7
c. 1dw $r2 = 4[$r4]
D. stw 12[$r8] = $r2
Instruction Latency
add
sub
1dw
stw
mpy
2
2
5
7
4
1. What is the CPI for sequential execution of the code with no data speculation?
2. Create a new schedule to maximize instruction level parallelism (ILP) using instruction scheduling and data speculation, but without
register renaming.
o Please maintain the original ordering of the instructions. Make sure you include appropriate latencies in the provided schedule.
o Calculate the new CPI, assuming no data speculation overhead and that the two locations did not collide

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Question 20 Consider two different machines with two different instruction sets, both of which have a clock rate of 800 MHz. The following measurements are recorded on the two machines running a given set of benchmark programs. Instruction Type Machine A Arithmetic and logic Load and store Branch Others Machine B Arithmetic and logic Load and store Branch Others O 50 ms O 70 ms O 55.2 ms O 60 ms Instruction Count (millions) O None of them 8 4 2 4 10 8 2 4 Cycles per Instruction 1 3 4 With machine A, how long would it take to execute the program? 3 1 2 4 3
3 C language into LC-3 Assembly Language
I need help question
Consider two different implementations, M1 and M2, of the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2 has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies (for a typical program) are as follow on the table. (a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2
E In the following code block(Reference:Q11), you will a set of assembly instructions with corresponding line numbers (line numbers are for informational purpose only and they are not part of the source code). 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mov edx, 5 dec ecx jmp LABEL1 mov eax, 1 LABEL1: mul edx jmp ecx mov edx, 0678h sub edx, eax jmp DWORD PTR [edx] neg ebx add ecx, ebx mov eax, 0 For each of the conditions/scenario listed below, indicate the corresponding line number (that cause or is associated with the condition/scenario). Enter 0 (Zero) if the condition is not caused by the block of code. 1) Memory indirect jump: type your answer... type your answer... type your answer... type your answer... 2) Register indirect jump: 3) Relative short jump: type your answer... 5) Two's complement type your answer... 4) Relative near jump: 6) Unreachable code