a) Briefly describe the key “architecture” feature of each of these types of technologies: DSP, GPU, FPGA. b) With reference to the diagram below, determine the logic levels of the control bits and then describe how the CBZ instruction is executed. (See the image) PCAddReadaddressInstruction[31-0]InstructionmemoryInstruction [31-21]Instruction [9-5]Instruction [20-16]Instruction [4-0]Instruction [31-0]ControlReg2LocBranchMemReadMemtoRegALUOPMemWriteALUSrcRegWriteReadregister 1 Readdata 1Readregister 2WriteReadregister data 2Writedata Registers32Sign-extend64Instruction [31-21]Shiftleft 2/OMIXALUAdd resultZeroALU ALUresultALUcontrolEUXAddress ReaddataWrite Datadata memoryMUX

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Computer Science

Briefly describe the key “architecture” feature of each of these types of technologies: DSP, GPU, FPGA.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter10: Application Development

Section: Chapter Questions

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Concept explainers

Transmission media

A communication channel that transmits data from a source to a recipient is referred to as "transmission media." Electromagnetic impulses are used to transmit data. Transmission media's primary purpose is to transmit data in the form of bits via a local area network (LAN). In data transport, it is the physical link that connects the transmitter and receiver. Transmission medium is part of layer 1 or physical layer of the ISO/OSI (Open System Interconnection) model.

Question

a) Briefly describe the key “architecture” feature of each of these types of technologies: DSP, GPU, FPGA.

b) With reference to the diagram below, determine the logic levels of the control bits and then describe how the CBZ instruction is executed. (See the image)

PC
Add
Read
address
Instruction
[31-0]
Instruction
memory
Instruction [31-21]
Instruction [9-5]
Instruction [20-16]
Instruction [4-0]
Instruction [31-0]
Control
Reg2Loc
Branch
MemRead
MemtoReg
ALUOP
MemWrite
ALUSrc
RegWrite
Read
register 1 Read
data 1
Read
register 2
Write
Read
register data 2
Write
data Registers
32
Sign-
extend
64
Instruction [31-21]
Shift
left 2/
OMIX
ALU
Add result
Zero
ALU ALU
result
ALU
control
EUX
Address Read
data
Write Data
data memory
MUX

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