I need someone to explain me step by step ( in a simple way) how does this microcontroller works or how to interprete the diagram. it will help if you can define some of the items like working register , ALU, mux do and what they are for?

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I need someone to explain me step by step ( in a simple way) how does this microcontroller works or how to interprete the diagram. it will help if you can define some of the items like working register , ALU, mux do and what they are for? 

The PIC 12F508/509 block diagram
Program memory
Data bus for
program
memory,
carrying
instruction
word
Address
extracted
from
instruction
word
Literal data
extracted from
instru wo
Program 12.
Bus
Instruction
itself!
Flash
512 x 12 or
1024 x 12
OSC1/CLKIN
OSC2
Program
Memory
Instruction Reg
Instruction
Decode & ²
Control
Timing
Generation
Internal RC
OSC
12
Address bus for
program memory
Program Counter
Stack 1
Stack 2
Direct Addr 5
Device Reset
Timer
Multiplexer
Working register
Power-on
Reset
Watchdog
Timer
MCLR ×
VDD, VSS
Key (See also Key to Figure 1.11)
FSR:
File Select Register
MUX:
W reg:
I
41x8
File
Registers
RAM Addr9+
Addr MUX
I
GPIO:
RC:
Data Bus
8
RAM
25 x 8 or
ALU
5-7 Addr
FSR Reg
Status RegE
MUX
W Reg
Data
memory
Indirect
8
Timero
GPIO
Input/
output
Address bus for
data memory
GPO/ISCPDAT
GP1/ISCPCLK
GP2/TOCKI
GP3/MCLR/VPP
GP4/OSC2
GP5/OSC1/CLKIN
Data bus for data
memory and
peripherals
The CPU
General-Purpose Input/Output
Resistor capacitor
Transcribed Image Text:The PIC 12F508/509 block diagram Program memory Data bus for program memory, carrying instruction word Address extracted from instruction word Literal data extracted from instru wo Program 12. Bus Instruction itself! Flash 512 x 12 or 1024 x 12 OSC1/CLKIN OSC2 Program Memory Instruction Reg Instruction Decode & ² Control Timing Generation Internal RC OSC 12 Address bus for program memory Program Counter Stack 1 Stack 2 Direct Addr 5 Device Reset Timer Multiplexer Working register Power-on Reset Watchdog Timer MCLR × VDD, VSS Key (See also Key to Figure 1.11) FSR: File Select Register MUX: W reg: I 41x8 File Registers RAM Addr9+ Addr MUX I GPIO: RC: Data Bus 8 RAM 25 x 8 or ALU 5-7 Addr FSR Reg Status RegE MUX W Reg Data memory Indirect 8 Timero GPIO Input/ output Address bus for data memory GPO/ISCPDAT GP1/ISCPCLK GP2/TOCKI GP3/MCLR/VPP GP4/OSC2 GP5/OSC1/CLKIN Data bus for data memory and peripherals The CPU General-Purpose Input/Output Resistor capacitor
Expert Solution
Step 1

High performance PIC12F508/509 the device can be attributed to a number of architectural functions commonly used in RISC microprocessors. First the PIC12F508/509 devices use the Harvard architecture in which program and data are accessible by separate buses. This is getting better bandwidth over traditional von Neumann architectures where program and data are downloaded to same bus Further, the separation of program and data memory allows instructions to be different in size from 8-bit data word. Instruction opcodes are 12-bit
wide, which makes it possible to have all monosyllabic instruction. 12-bit access to program memory the bus loads a 12-bit instruction in a single cycle and a two-phase pipeline overlaps loading and execution instruction. As a result, all instructions (33) run in one cycle (200 ns @ 20 MHz, 1 μs @ 4 MHz) except for program branches.

Table below lists program memory (Flash) and data memory (RAM) for the PIC12F508/509 devices

Device Memory
  Program  Data
PIC12F508   512 x 12 25 x 8
PIC12F509 1024 x 12  41 x 8
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