Below are one-bit inputs as M, X and Y and one each for T / F and E / B A logic circuit with one-bit output is shown in block. In the above combinational logic circuit, using the M input, X and Y inputs, what the circuit is determines that it will perform such a transaction. This circuit is X + Y when M = 0, X-Y when M = 1 performs its operations. At the exit, when M = 0, the total result is obtained at the T / F output. output is shown at the E / B output. The difference resulting from subtraction when M = 1 is at the T / F output, debt outflow is seen in the E / B outlet. Accordingly, the part with a question mark in the above box; a) Design with 4X1 data selector (multiplexer, mux) element (s). b) Design with 2X4 decoder element (s). Has 2X4 decoder element enable (EN) input
Below are one-bit inputs as M, X and Y and one each for T / F and E / B
A logic circuit with one-bit output is shown in block.
In the above combinational logic circuit, using the M input, X and Y inputs, what the circuit is
determines that it will perform such a transaction. This circuit is X + Y when M = 0, X-Y when M = 1
performs its operations. At the exit, when M = 0, the total result is obtained at the T / F output.
output is shown at the E / B output. The difference resulting from subtraction when M = 1 is at the T / F output,
debt outflow is seen in the E / B outlet. Accordingly, the part with a question mark in the above box;
a) Design with 4X1 data selector (multiplexer, mux) element (s).
b) Design with 2X4 decoder element (s).
Has 2X4 decoder element enable (EN) input
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