Behavioural Up Counter With Max Design and implement a 8-bit resetable up count, that stops counting when max is reached. The ports are: module counter( output u8_t count, input u8_t max, input logic clk, reset); The u8_t type is defined in the test bench. count is the counter's output. The counter should increment by one for even positive edge clock until the max is reached. The counter should not increment when max is reached. The counter is reset if reset = 1 when a positive edge clock occurs. The 8-bit comparator module, cmp, must be used to check when max is reached. The test bench will set max to 150 for its testing. Editor // include cmp module module counter( output u8_t count, input u8_t max, input logic clk, reset); logic m_test; cmp test(m_test, count, max); // complete the rest endmodule
Behavioural Up Counter With Max Design and implement a 8-bit resetable up count, that stops counting when max is reached. The ports are: module counter( output u8_t count, input u8_t max, input logic clk, reset); The u8_t type is defined in the test bench. count is the counter's output. The counter should increment by one for even positive edge clock until the max is reached. The counter should not increment when max is reached. The counter is reset if reset = 1 when a positive edge clock occurs. The 8-bit comparator module, cmp, must be used to check when max is reached. The test bench will set max to 150 for its testing. Editor // include cmp module module counter( output u8_t count, input u8_t max, input logic clk, reset); logic m_test; cmp test(m_test, count, max); // complete the rest endmodule
Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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Behavioural Up Counter With Max
Design and implement a 8-bit resetable up count, that stops counting when max is reached. The ports are:
module counter( output u8_t count, input u8_t max, input logic clk, reset);
The u8_t type is defined in the test bench. count is the counter's output. The counter should increment by one for even positive edge clock until the max is reached. The counter should not increment when max is reached. The counter is reset if reset = 1 when a positive edge clock occurs.
The 8-bit comparator module, cmp, must be used to check when max is reached. The test bench will set max to 150 for its testing.
Editor
// include cmp module
module counter( output u8_t count, input u8_t max,
input logic clk, reset);
logic m_test;
cmp test(m_test, count, max);
// complete the rest
endmodule
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