B3 A; В, А B A1 Bo Ao M C FA FA FA FA So V HDL Example 4.2 (Hierarchical Modeling-Eight-Bit Adder) Verilog At the bottom of the design hierarchy shown in Eig. 4.33 a half adder is composed of primitive gates. At the next level of the hierarchy, a full adder is formed by instantiating and connecting a pair of half adders. The third module describes the eight-bit adder by instantiating and linking together two four-bit adders. This example illustrates optional Verilog 2001, 2005 syntax, which eliminates extra typing of identifiers declaring the mode (e.g., output), type (reg), and declaration of a vector range (e.g, [3: 0]) of a port. The first version of the standard (1995) uses separate statements for these declarations; the revised standard includes the declarations within the port. module Add_half (input a, b, output c_out, sum), xor G1(sum, a, b); and 62(c_out, a, b); endnodule // Gate instance names are option module Add_full (input a, b, c_in, out put c_out, sum); Eig. 4.8 // see // wi is c_out; w2 is sum wire wi, W2, wa; Add_half M1 (a, b, wi, w2); Add_half MO (w2, e_in, w3, sum); or (c_out, w1, w3); endnodule module Add_rca_4, (input [3:0] a, b, input c_in output c_out, ou wire c_ini, c_in3, c_in4; Add_full MO (a[0), b[0), c_in, cini, sun[e]); Add_full M1 (a[ij, b(aj, c_ini, c_in2, sum[1]); Add_full M2 (a[2j, b(2), c_in2, c_in3, sum[2]); Add_full M3 (ataj, b(aj, c_ina, c_out, sum[3]); endnodule // İntermediate carries module Add_rca_8 (input [7:e] a, b, input c_in, output c_out, a wire c_in4; Add_rca_4 MO (a[3:0], b[3:0], c_in, c_in4, sum[3:0]); Add_rca_4 M1 (a[7:4], b[7:4], cin4, c_out, sum[7:4]); endnodule Verilog modules can be instantiated within other modules, but module declarations cannot be nested; that is, a module declaration cannot be inserted into the text between the module and endmodule keywords of another module. Also, instance names (e.g., MO) must be specified when a module is instantiated within another module.
B3 A; В, А B A1 Bo Ao M C FA FA FA FA So V HDL Example 4.2 (Hierarchical Modeling-Eight-Bit Adder) Verilog At the bottom of the design hierarchy shown in Eig. 4.33 a half adder is composed of primitive gates. At the next level of the hierarchy, a full adder is formed by instantiating and connecting a pair of half adders. The third module describes the eight-bit adder by instantiating and linking together two four-bit adders. This example illustrates optional Verilog 2001, 2005 syntax, which eliminates extra typing of identifiers declaring the mode (e.g., output), type (reg), and declaration of a vector range (e.g, [3: 0]) of a port. The first version of the standard (1995) uses separate statements for these declarations; the revised standard includes the declarations within the port. module Add_half (input a, b, output c_out, sum), xor G1(sum, a, b); and 62(c_out, a, b); endnodule // Gate instance names are option module Add_full (input a, b, c_in, out put c_out, sum); Eig. 4.8 // see // wi is c_out; w2 is sum wire wi, W2, wa; Add_half M1 (a, b, wi, w2); Add_half MO (w2, e_in, w3, sum); or (c_out, w1, w3); endnodule module Add_rca_4, (input [3:0] a, b, input c_in output c_out, ou wire c_ini, c_in3, c_in4; Add_full MO (a[0), b[0), c_in, cini, sun[e]); Add_full M1 (a[ij, b(aj, c_ini, c_in2, sum[1]); Add_full M2 (a[2j, b(2), c_in2, c_in3, sum[2]); Add_full M3 (ataj, b(aj, c_ina, c_out, sum[3]); endnodule // İntermediate carries module Add_rca_8 (input [7:e] a, b, input c_in, output c_out, a wire c_in4; Add_rca_4 MO (a[3:0], b[3:0], c_in, c_in4, sum[3:0]); Add_rca_4 M1 (a[7:4], b[7:4], cin4, c_out, sum[7:4]); endnodule Verilog modules can be instantiated within other modules, but module declarations cannot be nested; that is, a module declaration cannot be inserted into the text between the module and endmodule keywords of another module. Also, instance names (e.g., MO) must be specified when a module is instantiated within another module.
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Question
Write the HDL gate-level hierarchical description of a four-bit adder–subtractor for unsigned binary numbers. The circuit is similar to Fig. 4.13 but without output V. You can instantiate the four-bit full adder described in HDL Example 4.2 .
Transcribed Image Text:B3
A;
В, А
B A1
Bo
Ao
M
C
FA
FA
FA
FA
So
V
![HDL Example 4.2 (Hierarchical
Modeling-Eight-Bit Adder)
Verilog
At the bottom of the design hierarchy shown in Eig. 4.33 a half adder is
composed of primitive gates. At the next level of the hierarchy, a full
adder is formed by instantiating and connecting a pair of half adders. The
third module describes the eight-bit adder by instantiating and linking
together two four-bit adders. This example illustrates optional Verilog
2001, 2005 syntax, which eliminates extra typing of identifiers declaring
the mode (e.g., output), type (reg), and declaration of a vector range (e.g,
[3: 0]) of a port. The first version of the standard (1995) uses separate
statements for these declarations; the revised standard includes the
declarations within the port.
module Add_half (input a, b, output c_out, sum),
xor G1(sum, a, b);
and 62(c_out, a, b);
endnodule
// Gate instance names are option
module Add_full (input a, b, c_in, out put c_out, sum);
Eig.
4.8
// see
// wi is c_out; w2 is sum
wire wi, W2, wa;
Add_half M1 (a, b, wi, w2);
Add_half MO (w2, e_in, w3, sum);
or (c_out, w1, w3);
endnodule
module Add_rca_4, (input [3:0] a, b, input c_in output c_out, ou
wire c_ini, c_in3, c_in4;
Add_full MO (a[0), b[0), c_in, cini, sun[e]);
Add_full M1 (a[ij, b(aj, c_ini, c_in2, sum[1]);
Add_full M2 (a[2j, b(2), c_in2, c_in3, sum[2]);
Add_full M3 (ataj, b(aj, c_ina, c_out, sum[3]);
endnodule
// İntermediate carries
module Add_rca_8 (input [7:e] a, b, input c_in, output c_out, a
wire c_in4;
Add_rca_4 MO (a[3:0], b[3:0], c_in, c_in4, sum[3:0]);
Add_rca_4 M1 (a[7:4], b[7:4], cin4, c_out, sum[7:4]);
endnodule
Verilog modules can be instantiated within other modules, but module
declarations cannot be nested; that is, a module declaration cannot be
inserted into the text between the module and endmodule keywords of
another module. Also, instance names (e.g., MO) must be specified when a
module is instantiated within another module.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F722c0a28-3cf8-4322-9159-01ebd4b63956%2F07f4ca0c-7feb-4dbb-98a9-be324b387a1b%2Fsz3dtsf_processed.png&w=3840&q=75)
Transcribed Image Text:HDL Example 4.2 (Hierarchical
Modeling-Eight-Bit Adder)
Verilog
At the bottom of the design hierarchy shown in Eig. 4.33 a half adder is
composed of primitive gates. At the next level of the hierarchy, a full
adder is formed by instantiating and connecting a pair of half adders. The
third module describes the eight-bit adder by instantiating and linking
together two four-bit adders. This example illustrates optional Verilog
2001, 2005 syntax, which eliminates extra typing of identifiers declaring
the mode (e.g., output), type (reg), and declaration of a vector range (e.g,
[3: 0]) of a port. The first version of the standard (1995) uses separate
statements for these declarations; the revised standard includes the
declarations within the port.
module Add_half (input a, b, output c_out, sum),
xor G1(sum, a, b);
and 62(c_out, a, b);
endnodule
// Gate instance names are option
module Add_full (input a, b, c_in, out put c_out, sum);
Eig.
4.8
// see
// wi is c_out; w2 is sum
wire wi, W2, wa;
Add_half M1 (a, b, wi, w2);
Add_half MO (w2, e_in, w3, sum);
or (c_out, w1, w3);
endnodule
module Add_rca_4, (input [3:0] a, b, input c_in output c_out, ou
wire c_ini, c_in3, c_in4;
Add_full MO (a[0), b[0), c_in, cini, sun[e]);
Add_full M1 (a[ij, b(aj, c_ini, c_in2, sum[1]);
Add_full M2 (a[2j, b(2), c_in2, c_in3, sum[2]);
Add_full M3 (ataj, b(aj, c_ina, c_out, sum[3]);
endnodule
// İntermediate carries
module Add_rca_8 (input [7:e] a, b, input c_in, output c_out, a
wire c_in4;
Add_rca_4 MO (a[3:0], b[3:0], c_in, c_in4, sum[3:0]);
Add_rca_4 M1 (a[7:4], b[7:4], cin4, c_out, sum[7:4]);
endnodule
Verilog modules can be instantiated within other modules, but module
declarations cannot be nested; that is, a module declaration cannot be
inserted into the text between the module and endmodule keywords of
another module. Also, instance names (e.g., MO) must be specified when a
module is instantiated within another module.
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