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Datapath Control line functions: The functions provided by each GPLB in the ALU: Signal Active High/low Description RDA_A H RDA_B H LDA_A H LDA_B H Read contents of A Reg on to A Bus Read contents of A Reg on to B Bus Write contents of A Bus into A Reg Write contents of B Bus into A Reg CO C1 C2 C3 0000 1 0 00 A.B 0 1 00 A.B 1100 AB+ AB A.B 0 0 1 0 Function Result 0 (A+B) A.B B A.B RDB_A H Read contents of B Reg on to A Bus 1 010 A.B+A.B A RDB_B H Read contents of B Reg on to B Bus 0 1 10 A.B + A.B A exor B LDB_A H Write contents of A Bus into B Reg 1 1 10 A.B+ A.B+ A.B A.B LDB_B LD_ALU H RD_ALU_A H RD_ALU_B H SELECT A H H Write contents of B Bus into B Reg 0 0 01 A.B A.B Write output of ALU Bus into ALU Reg 1001 A.B+Ā.B A exnor B Read contents of ALU Reg on to A Bus Read contents of ALU Reg on to B Bus Select A Bus into ALU 0101 A.B+ A.B A 1 1 0 1 A.B+A.B+A.B A+B 0 0 11 A.B+Ā.B B CO-C3 CO-C3' CO"-C3" H H General Purpose Logic Block 1 Control Signals 1 0 1 1 A.B+ A.B+ A.B A+B H General Purpose Logic Block 2 Control Signals 0 1 1 1 A.B+A.B+ A.B A+B General Purpose Logic Block 3 Control Signals 1 1 1 1 A.B+A.B+ A.B+ A.B 1 Block Diagram of ALU: Co C1 C2 C3 Cin-1 A- Logic Block 1 Propagate P Sum Logic Block 3 Sum Manchester Carry C"C"C"C"3 B₁ Logic Block 2 G Generate C'o C' C'₂ C's Cout Processor Instruction Set: Mnemonic Description Instruction Code (Opcode) INSTA INSTB INSTC A

Datapath Control line functions: The functions provided by each GPLB in the ALU: Signal Active High/low Description RDA_A H RDA_B H LDA_A H LDA_B H Read contents of A Reg on to A Bus Read contents of A Reg on to B Bus Write contents of A Bus into A Reg Write contents of B Bus into A Reg CO C1 C2 C3 0000 1 0 00 A.B 0 1 00 A.B 1100 AB+ AB A.B 0 0 1 0 Function Result 0 (A+B) A.B B A.B RDB_A H Read contents of B Reg on to A Bus 1 010 A.B+A.B A RDB_B H Read contents of B Reg on to B Bus 0 1 10 A.B + A.B A exor B LDB_A H Write contents of A Bus into B Reg 1 1 10 A.B+ A.B+ A.B A.B LDB_B LD_ALU H RD_ALU_A H RD_ALU_B H SELECT A H H Write contents of B Bus into B Reg 0 0 01 A.B A.B Write output of ALU Bus into ALU Reg 1001 A.B+Ā.B A exnor B Read contents of ALU Reg on to A Bus Read contents of ALU Reg on to B Bus Select A Bus into ALU 0101 A.B+ A.B A 1 1 0 1 A.B+A.B+A.B A+B 0 0 11 A.B+Ā.B B CO-C3 CO-C3' CO"-C3" H H General Purpose Logic Block 1 Control Signals 1 0 1 1 A.B+ A.B+ A.B A+B H General Purpose Logic Block 2 Control Signals 0 1 1 1 A.B+A.B+ A.B A+B General Purpose Logic Block 3 Control Signals 1 1 1 1 A.B+A.B+ A.B+ A.B 1 Block Diagram of ALU: Co C1 C2 C3 Cin-1 A- Logic Block 1 Propagate P Sum Logic Block 3 Sum Manchester Carry C"C"C"C"3 B₁ Logic Block 2 G Generate C'o C' C'₂ C's Cout Processor Instruction Set: Mnemonic Description Instruction Code (Opcode) INSTA INSTB INSTC A

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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Please can you solve this question in a step by step form correctly, please look at the refernces provided on the data path control lines, the GPLB functions, the processor instruction set

Datapath Control line functions: The functions provided by each GPLB in the ALU: Signal Active High/low Description RDA_A H RDA_B H LDA_A H LDA_B H Read contents of A Reg on to A Bus Read contents of A Reg on to B Bus Write contents of A Bus into A Reg Write contents of B Bus into A Reg CO C1 C2 C3 0000 1 0 00 A.B 0 1 00 A.B 1100 AB+ AB A.B 0 0 1 0 Function Result 0 (A+B) A.B B A.B RDB_A H Read contents of B Reg on to A Bus 1 010 A.B+A.B A RDB_B H Read contents of B Reg on to B Bus 0 1 10 A.B + A.B A exor B LDB_A H Write contents of A Bus into B Reg 1 1 10 A.B+ A.B+ A.B A.B LDB_B LD_ALU H RD_ALU_A H RD_ALU_B H SELECT A H H Write contents of B Bus into B Reg 0 0 01 A.B A.B Write output of ALU Bus into ALU Reg 1001 A.B+Ā.B A exnor B Read contents of ALU Reg on to A Bus Read contents of ALU Reg on to B Bus Select A Bus into ALU 0101 A.B+ A.B A 1 1 0 1 A.B+A.B+A.B A+B 0 0 11 A.B+Ā.B B CO-C3 CO-C3' CO"-C3" H H General Purpose Logic Block 1 Control Signals 1 0 1 1 A.B+ A.B+ A.B A+B H General Purpose Logic Block 2 Control Signals 0 1 1 1 A.B+A.B+ A.B A+B General Purpose Logic Block 3 Control Signals 1 1 1 1 A.B+A.B+ A.B+ A.B 1 Block Diagram of ALU: Co C1 C2 C3 Cin-1 A- Logic Block 1 Propagate P Sum Logic Block 3 Sum Manchester Carry C"C"C"C"3 B₁ Logic Block 2 G Generate C'o C' C'₂ C's Cout Processor Instruction Set: Mnemonic Description Instruction Code (Opcode) INSTA INSTB INSTC A<A+B Add 0 0 1 A<A-B Subtract 0 1 0 A <A AND B NAND 0 1 1 A<Ā OR B A OR B 1 0 0 A <A AND B A<A B AND 1 0 1 XNOR 1 1 0
Transcribed Image Text:Datapath Control line functions: The functions provided by each GPLB in the ALU: Signal Active High/low Description RDA_A H RDA_B H LDA_A H LDA_B H Read contents of A Reg on to A Bus Read contents of A Reg on to B Bus Write contents of A Bus into A Reg Write contents of B Bus into A Reg CO C1 C2 C3 0000 1 0 00 A.B 0 1 00 A.B 1100 AB+ AB A.B 0 0 1 0 Function Result 0 (A+B) A.B B A.B RDB_A H Read contents of B Reg on to A Bus 1 010 A.B+A.B A RDB_B H Read contents of B Reg on to B Bus 0 1 10 A.B + A.B A exor B LDB_A H Write contents of A Bus into B Reg 1 1 10 A.B+ A.B+ A.B A.B LDB_B LD_ALU H RD_ALU_A H RD_ALU_B H SELECT A H H Write contents of B Bus into B Reg 0 0 01 A.B A.B Write output of ALU Bus into ALU Reg 1001 A.B+Ā.B A exnor B Read contents of ALU Reg on to A Bus Read contents of ALU Reg on to B Bus Select A Bus into ALU 0101 A.B+ A.B A 1 1 0 1 A.B+A.B+A.B A+B 0 0 11 A.B+Ā.B B CO-C3 CO-C3' CO"-C3" H H General Purpose Logic Block 1 Control Signals 1 0 1 1 A.B+ A.B+ A.B A+B H General Purpose Logic Block 2 Control Signals 0 1 1 1 A.B+A.B+ A.B A+B General Purpose Logic Block 3 Control Signals 1 1 1 1 A.B+A.B+ A.B+ A.B 1 Block Diagram of ALU: Co C1 C2 C3 Cin-1 A- Logic Block 1 Propagate P Sum Logic Block 3 Sum Manchester Carry C"C"C"C"3 B₁ Logic Block 2 G Generate C'o C' C'₂ C's Cout Processor Instruction Set: Mnemonic Description Instruction Code (Opcode) INSTA INSTB INSTC A<A+B Add 0 0 1 A<A-B Subtract 0 1 0 A <A AND B NAND 0 1 1 A<Ā OR B A OR B 1 0 0 A <A AND B A<A B AND 1 0 1 XNOR 1 1 0
(b) Design the State Table and State Diagram of a state machine to control the data path shown in FIG.1 during the execution of the operation: A < A OR B Note: The symbol '<' is read as "becomes". A and B represent the contents of register A and register B in the data path respectively.
Transcribed Image Text:(b) Design the State Table and State Diagram of a state machine to control the data path shown in FIG.1 during the execution of the operation: A < A OR B Note: The symbol '<' is read as "becomes". A and B represent the contents of register A and register B in the data path respectively.
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