Homework Help is Here – Start Your Trial Now!
Engineering
Computer Engineering
Assume the PC has the address 0x021A when FETCH INSTRUCTION phase begins. After that first instruction executes, which one describes the second instruction to execute? a) LDR R4 with a value from memory b) LDR R5 with a value from memory c) ADD R4 to R5 and save result in R7 d)

Assume the PC has the address 0x021A when FETCH INSTRUCTION phase begins. After that first instruction executes, which one describes the second instruction to execute? a) LDR R4 with a value from memory b) LDR R5 with a value from memory c) ADD R4 to R5 and save result in R7 d)

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
See similar textbooks
icon
Related questions
Question
100%

Assume the PC has the address 0x021A when FETCH INSTRUCTION phase begins. After that first instruction executes, which one describes the second instruction to execute?

a) LDR R4 with a value from memory

b) LDR R5 with a value from memory

c) ADD R4 to R5 and save result in R7

d) 

The following assumes the LC-3 architecture. Consider the following table that represents several of the 16-bit registers in the register file: | Register | CONTENTS (binary) | |----------|-----------------------| | R0 | 0000 0011 0001 1110 | | R1 | 0000 0011 0010 0000 | | R2 | 0000 0011 0010 0001 | | ... | ... | Also consider the following table that represents part of the memory of a 16-bit address space that has an addressability of 2 bytes: | ADDRESS (hex) | CONTENTS (binary) | |---------------|--------------------------| | ... | ... | | 0x0321 | 0001 1111 0000 0101 | | 0x0320 | 0001 1111 0100 0110 | | 0x031F | 0110 1010 1100 0100 | | 0x031E | 0110 1000 1101 0101 | | ... | ... | | 0x021C | 1100 0000 0000 0000 | | 0x021B | 1100 0000 1000 0000 | | 0x021A | 1100 0000 0100 0000 | | ... | ... | Assume the PC has the address 0x021A when the FETCH INSTRUCTION phase begins. After that first instruction executes, which one describes the second instruction to execute?
Transcribed Image Text:The following assumes the LC-3 architecture. Consider the following table that represents several of the 16-bit registers in the register file: | Register | CONTENTS (binary) | |----------|-----------------------| | R0 | 0000 0011 0001 1110 | | R1 | 0000 0011 0010 0000 | | R2 | 0000 0011 0010 0001 | | ... | ... | Also consider the following table that represents part of the memory of a 16-bit address space that has an addressability of 2 bytes: | ADDRESS (hex) | CONTENTS (binary) | |---------------|--------------------------| | ... | ... | | 0x0321 | 0001 1111 0000 0101 | | 0x0320 | 0001 1111 0100 0110 | | 0x031F | 0110 1010 1100 0100 | | 0x031E | 0110 1000 1101 0101 | | ... | ... | | 0x021C | 1100 0000 0000 0000 | | 0x021B | 1100 0000 1000 0000 | | 0x021A | 1100 0000 0100 0000 | | ... | ... | Assume the PC has the address 0x021A when the FETCH INSTRUCTION phase begins. After that first instruction executes, which one describes the second instruction to execute?
**Task Overview:** Assume the PC has the address 0x021A when the FETCH INSTRUCTION phase begins. After that first instruction executes, which one describes the second instruction to execute? **REFERENCE:** **Table of LC-3 Instructions:** | Opcode | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |--------|----|----|----|----|----|----|----|----|----|----|---|----|----|----|----|----| | ADD | 0 | 0 | 0 | 1 | DST| SRC1 | 0 | 0 | 0 | SRC2 | | JMP | 1 | 1 | 0 | 0 | 0 | Base | 0 | 0 | 0 | 0 | 0 | 0 | | LDR | 0 | 1 | 1 | 0 | DST| Base | Offset | **Answer Choices:** - ○ LDR R4 with a value from memory - ○ LDR R5 with a value from memory - ○ ADD R4 to R5 and save result in R7 - ○ ADD R5 to R6 and save result in R7 **Diagram Explanation:** The table outlines the instruction set for a hypothetical LC-3 processor, showing how the bits in an instruction word determine the operation to perform. The instruction consists of an opcode field defined by bits 15 to 12, followed by operand fields. 1. **ADD Instruction:** - Bits 15-12 are `0001` - The instruction formats an addition operation with destination (`DST`), and source registers (`SRC1` and `SRC2`). 2. **JMP Instruction:** - Bits 15-12 are `1100` - Used for jumping to a location specified by a base register (`Base`). 3. **LDR Instruction:** - Bits 15-12 are `0110` - Loads a value from memory into a destination register (`DST`) using the base register (`Base`)
Transcribed Image Text:**Task Overview:** Assume the PC has the address 0x021A when the FETCH INSTRUCTION phase begins. After that first instruction executes, which one describes the second instruction to execute? **REFERENCE:** **Table of LC-3 Instructions:** | Opcode | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |--------|----|----|----|----|----|----|----|----|----|----|---|----|----|----|----|----| | ADD | 0 | 0 | 0 | 1 | DST| SRC1 | 0 | 0 | 0 | SRC2 | | JMP | 1 | 1 | 0 | 0 | 0 | Base | 0 | 0 | 0 | 0 | 0 | 0 | | LDR | 0 | 1 | 1 | 0 | DST| Base | Offset | **Answer Choices:** - ○ LDR R4 with a value from memory - ○ LDR R5 with a value from memory - ○ ADD R4 to R5 and save result in R7 - ○ ADD R5 to R6 and save result in R7 **Diagram Explanation:** The table outlines the instruction set for a hypothetical LC-3 processor, showing how the bits in an instruction word determine the operation to perform. The instruction consists of an opcode field defined by bits 15 to 12, followed by operand fields. 1. **ADD Instruction:** - Bits 15-12 are `0001` - The instruction formats an addition operation with destination (`DST`), and source registers (`SRC1` and `SRC2`). 2. **JMP Instruction:** - Bits 15-12 are `1100` - Used for jumping to a location specified by a base register (`Base`). 3. **LDR Instruction:** - Bits 15-12 are `0110` - Loads a value from memory into a destination register (`DST`) using the base register (`Base`)
Expert Solution
trending now

Trending now

This is a popular solution!

steps

Step by step

Solved in 2 steps

SEE SOLUTIONCheck out a sample Q&A here
Blurred answer
Recommended textbooks for you
Computer Networking: A Top-Down Approach (7th Edi…
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Concepts of Database Management
Concepts of Database Management
Computer Engineering
ISBN:
9781337093422
Author:
Joy L. Starks, Philip J. Pratt, Mary Z. Last
Publisher:
Cengage Learning
Prelude to Programming
Prelude to Programming
Computer Engineering
ISBN:
9780133750423
Author:
VENIT, Stewart
Publisher:
Pearson Education
Sc Business Data Communications and Networking, T…
Sc Business Data Communications and Networking, T…
Computer Engineering
ISBN:
9781119368830
Author:
FITZGERALD
Publisher:
WILEY
SEE MORE TEXTBOOKS