Assume that you have a system that contains a 16-word cache (C-16). Consider the following RISCV assembly codeaddi to, zero, 4addi so, zero, 0loop: beq to, zero, doneIw tl, Ox30(s0)Iw t2, 0x70(s0)lw t3, 0x54(s0)Iw t3, 0x50(s0)addi to, to, -1j loopdone:Partl: Direct Mapped Cache, b = 1 word1) Fill in the correct size for the cache fields (Assume 32-bit memory address size):TagSet2)Place every instruction's data in the correct set in the cache. Also, determine what kind of miss the instruction faces.Instruction's datamem[0x00.030]mem[0x00..070]Byte Offsetmem[0x00.054]mem[0x00..050]Set Cache No. Compulsory miss Conflict miss (2nd iteration)Answer as :0, 3, 5... Answer as: TRUE or FALSE Answer as: TRUE or FALSE3) Find the miss rate (NOTE: if the number is 88.777778, then your answer should be 88.8) :(Note: number of misses includes both compulsory and the conflict misses in all iterations)Cache miss rate=

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Assume that you have a system that contains a 16-word cache (C-16). Consider the following RISCV assembly code addi to, zero, 4 addi so, zero, 0 loop: beq to, zero, done Iw t1, 0x30(s0) lw t2, 0x70(s0) lw t3,0x54(s0) Iw t3,0x50(s0) addi to, t0, -1 j loop done: Partl: Direct Mapped Cache, b = 1 word 20

Assume that you have a system that contains a 16-word cache (C-16). Consider the following RISCV assembly code addi to, zero, 4 addi so, zero, 0 loop: beq to, zero, done Iw t1, 0x30(s0) lw t2, 0x70(s0) lw t3,0x54(s0) Iw t3,0x50(s0) addi to, t0, -1 j loop done: Partl: Direct Mapped Cache, b = 1 word 20

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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