Assume an instruction:  0x00c6ba23 is located in memory at address:  Answer the following questions when the instruction is executed based on the datapath and control shown in Figure 4.17. a). What are the values of the ALU Control to the ALU unit? b) What is the PC address after this instruction is executed? c)What is the values (either 0 or 1) of the control signals to the three multiplexers? d) What are the input values for the ALU?

C++ Programming: From Problem Analysis to Program Design
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 Assume an instruction:  0x00c6ba23 is located in memory at address:  Answer the following questions when the instruction is executed based on the datapath and control shown in Figure 4.17.

a). What are the values of the ALU Control to the ALU unit?

b) What is the PC address after this instruction is executed?

c)What is the values (either 0 or 1) of the control signals to the three multiplexers?

d) What are the input values for the ALU?

 

4.4 A Simple Implementation Scheme
257
Add
4
Add Sum
Shift
left 1
Branch
MemRead
MemtoReg
Instruction [6-0]
Control ALU0P
MemWrite
ALUSrc
RegWrite
Instruction [19-15]
Read
address
Read
register 1 Read
data 1
PC
Instruction [24-20]
Read
Zero
Instruction
register 2
[31-0]
ALU ALU
Read
Address data
Instruction [11-7]
Read
Write
register data 2
result
Instruction
memory
Write
data Registers
Data
Write
data memory
Instruction [31-0]
32
64
Imm
Gen
ALU
control
Instruction [30,14-12]
FIGURE 4.17 The simple datapath with the control unit. The input to the control unit is the 7-bit opcode field from the instruction.
The outputs of the control unit consist of two 1-bit signals that are used to control multiplexors (ALUSrc and MemtoReg), three signals for
controlling reads and writes in the register file and data memory (RegWrite, MemRead, and MemWrite), a 1-bit signal used in determining
whether to possibly branch (Branch), and a 2-bit control signal for the ALU (ALUOP). An AND gate is used to combine the branch control
signal and the Zero output from the ALU; the AND gate output controls the selection of the next PC. Notice that PCSrc is now a derived signal,
rather than one coming directly from the control unit. Thus, we drop the signal name in subsequent figures.
Transcribed Image Text:4.4 A Simple Implementation Scheme 257 Add 4 Add Sum Shift left 1 Branch MemRead MemtoReg Instruction [6-0] Control ALU0P MemWrite ALUSrc RegWrite Instruction [19-15] Read address Read register 1 Read data 1 PC Instruction [24-20] Read Zero Instruction register 2 [31-0] ALU ALU Read Address data Instruction [11-7] Read Write register data 2 result Instruction memory Write data Registers Data Write data memory Instruction [31-0] 32 64 Imm Gen ALU control Instruction [30,14-12] FIGURE 4.17 The simple datapath with the control unit. The input to the control unit is the 7-bit opcode field from the instruction. The outputs of the control unit consist of two 1-bit signals that are used to control multiplexors (ALUSrc and MemtoReg), three signals for controlling reads and writes in the register file and data memory (RegWrite, MemRead, and MemWrite), a 1-bit signal used in determining whether to possibly branch (Branch), and a 2-bit control signal for the ALU (ALUOP). An AND gate is used to combine the branch control signal and the Zero output from the ALU; the AND gate output controls the selection of the next PC. Notice that PCSrc is now a derived signal, rather than one coming directly from the control unit. Thus, we drop the signal name in subsequent figures.
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