a) Show the output waveform of a NAND gate with the inputs A, B, and C indicated in the figure below. A B C

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Question 4
a) Show the output waveform of a NAND gate with the inputs
A, B, and C indicated in the figure below.
A
C
b) A cache has been designed such that it has 1024 lines, with
each line or block containing 8 words. Determine the line
number, tag, and word position for the 20-bit address
3E9D216 using the direct mapping method.
c) The table below represents 10 lines from a 256 line cache
that uses direct mapping with a block size of 4 words.
Identify the address of the shaded data (8C16).
3
Line#
|Tag
Word 00
Word 01 Word 10 Word 11
10
110101 12
34
56
78
01010154
l000111 29
32
6A
D3
8C
A2
BC
12
ED
F3
3
001100 33
2C
C8
14
110011 9A
D8
FO
Transcribed Image Text:Question 4 a) Show the output waveform of a NAND gate with the inputs A, B, and C indicated in the figure below. A C b) A cache has been designed such that it has 1024 lines, with each line or block containing 8 words. Determine the line number, tag, and word position for the 20-bit address 3E9D216 using the direct mapping method. c) The table below represents 10 lines from a 256 line cache that uses direct mapping with a block size of 4 words. Identify the address of the shaded data (8C16). 3 Line# |Tag Word 00 Word 01 Word 10 Word 11 10 110101 12 34 56 78 01010154 l000111 29 32 6A D3 8C A2 BC 12 ED F3 3 001100 33 2C C8 14 110011 9A D8 FO
Question 5
Convert the IEEE Standard 754 number
01101011011100101000000000000000 to its binary
equivalent.
b) Determine the number of blocks of 8 words are there in a
256 MB memory space and draw the logical organization
of the full address identifying the block ID portion and the
word (offset) portion.
Determine the number of 256 KB memories can be placed
(without overlapping) in the memory space of a processor
that has 30 address lines.
Transcribed Image Text:Question 5 Convert the IEEE Standard 754 number 01101011011100101000000000000000 to its binary equivalent. b) Determine the number of blocks of 8 words are there in a 256 MB memory space and draw the logical organization of the full address identifying the block ID portion and the word (offset) portion. Determine the number of 256 KB memories can be placed (without overlapping) in the memory space of a processor that has 30 address lines.
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