A multi-input multi-output digital system as in figure (project x) has 4- inputs (a, b, c, d) with 2-outputs (y1, y2). A- Find the function of the outputs (y1, y2) in terms of inputs (a, b, c, d). B- Find the total cost using table (1). C- Redesign the system to minimize the cost using table (1). D- Redesign the system in C using NAND gates. E- Redesign the system using ROM and PLA. F-Prove the new design has same function for the original system. Table (1): The cost table Inputs AND, OR, 22 33 4 5 4 5 66 NAND, NOR XOR,XNOR 4 6 MUX 4 - Decoder 8 16 32 882 10 - - 64 - Other cost HA=6 FA=14 Z=1 NOT=0 8 8 12 16 16 66 a x1 a FA x2 b MUX x8 a x3 b FA FA x4 yl y2 1 d Decoder x5 x6 x7

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A multi-input multi-output digital system as in figure (project x) has 4-
inputs (a, b, c, d) with 2-outputs (y1, y2).
A- Find the function of the outputs (y1, y2) in terms of inputs (a, b, c, d).
B- Find the total cost using table (1).
C- Redesign the system to minimize the cost using table (1).
D- Redesign the system in C using NAND gates.
E- Redesign the system using ROM and PLA.
F-Prove the new design has same function for the original system.
Table (1): The cost table
Inputs
AND, OR,
22
33
4
5
4
5
66
NAND, NOR
XOR,XNOR
4
6
MUX
4
-
Decoder
8
16
32
882
10
-
-
64
-
Other cost
HA=6 FA=14 Z=1
NOT=0
8
8
12
16
16
66
a
x1
a
FA
x2
b
MUX
x8
a
x3
b
FA
FA
x4
yl
y2
1
d
Decoder
x5
x6
x7
Transcribed Image Text:A multi-input multi-output digital system as in figure (project x) has 4- inputs (a, b, c, d) with 2-outputs (y1, y2). A- Find the function of the outputs (y1, y2) in terms of inputs (a, b, c, d). B- Find the total cost using table (1). C- Redesign the system to minimize the cost using table (1). D- Redesign the system in C using NAND gates. E- Redesign the system using ROM and PLA. F-Prove the new design has same function for the original system. Table (1): The cost table Inputs AND, OR, 22 33 4 5 4 5 66 NAND, NOR XOR,XNOR 4 6 MUX 4 - Decoder 8 16 32 882 10 - - 64 - Other cost HA=6 FA=14 Z=1 NOT=0 8 8 12 16 16 66 a x1 a FA x2 b MUX x8 a x3 b FA FA x4 yl y2 1 d Decoder x5 x6 x7
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