A 5-V, 10-MHz oscillator having a rise/falltime of 10 ns and a 50% duty cycle is applied to a gate as shown in Fig. P3.2.4. Determine the value of the capacitance such that the fifth harmonic is reduced by 20 dB in the gate voltage VG(1). [63.34 pF]
A 5-V, 10-MHz oscillator having a rise/falltime of 10 ns and a 50% duty cycle is applied to a gate as shown in Fig. P3.2.4. Determine the value of the capacitance such that the fifth harmonic is reduced by 20 dB in the gate voltage VG(1). [63.34 pF]
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![3.2.4 A 5-V, 10-MHz oscillator having a rise/falltime of 10 ns and a 50% duty
cycle is applied to a gate as shown in Fig. P3.2.4. Determine the value of
the capacitance such that the fifth harmonic is reduced by 20 dB in the
gate voltage VG(1). [63.34 pF]
1 kQ
Vslt) +
Val1)
1 ko
Člock
Gate
L
FIGURE P3.2.4.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F8061f1e8-97b7-4405-a854-1725dbe4bdcc%2F4eab46b1-900b-4450-84e3-63ded0397d7e%2Fvjm3ijb_processed.png&w=3840&q=75)
Transcribed Image Text:3.2.4 A 5-V, 10-MHz oscillator having a rise/falltime of 10 ns and a 50% duty
cycle is applied to a gate as shown in Fig. P3.2.4. Determine the value of
the capacitance such that the fifth harmonic is reduced by 20 dB in the
gate voltage VG(1). [63.34 pF]
1 kQ
Vslt) +
Val1)
1 ko
Člock
Gate
L
FIGURE P3.2.4.
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