A 4-processor systems implements cache coherence with a snoopy MSI protocol. For each access in the sequence below (to the same BLOCK address), list the coherence states (M/S/I) for each processor's cache after the access. Assume all the cache states begin in the Invalid (I) state. Event P1 state P2 state P3 state P4 state P1 reads P1 writes P2 reads P4 reads

A 4-processor systems implements cache coherence with a snoopy MSI protocol. For each access in the sequence below (to the same BLOCK address), list the coherence states (M/S/I) for each processor's cache after the access. Assume all the cache states begin in the Invalid (I) state. Event P1 state P2 state P3 state P4 state P1 reads P1 writes P2 reads P4 reads

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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