4. Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of 64bytes each, and 4 page frames. Assuming the following page table, answer the questions below:Page01234567Frame # Valid Bit130210011000a) How many bits are in a virtual address?b) How many bits are in a physical address?e) What physical address corresponds to virtual addresses 0x00 and to 0x44?5. Consider a 4-drive, 200 GB-per-drive RAID array. What is the available data storage capacityfor each of the RAID levels 0, 1, 3, 4, 5, and 676. Consider a single-platter disk with the following parameters:Rotation speed - 7200 rpm;number of tracks on one side of platter - 30,000;Number of sectors per track - 600;Seek time-one ms for every hundred tracks traversed.Let the disk receive a request to access a random sector on a random track and assume thedisk head starts at track 0.a) What is the average seek time?b) What is the average rotational latency?e) What is the transfer time for a sector?

Name: 4. Suppose you have a byte-addressable virtual address memory system
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Description: 4. Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of 64bytes each, and 4 page frames. Assuming the following page table, answer the questions below:Page01234567Frame # Valid Bit130210011000a) How many bits are

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4. Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of 64 bytes each, and 4 page frames. Assuming the following page table, answer the questions below: Page 0 1 2 3 5 7 Frame # Valid Bit 1 1 3 0 0 1 1 0 0 0 0 2 a) How many bits are in a virtual address? b) How many bits are in a physical address? e) What physical address corresponds to virtual addresses 0x00 and to 0x447

4. Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of 64 bytes each, and 4 page frames. Assuming the following page table, answer the questions below: Page 0 1 2 3 5 7 Frame # Valid Bit 1 1 3 0 0 1 1 0 0 0 0 2 a) How many bits are in a virtual address? b) How many bits are in a physical address? e) What physical address corresponds to virtual addresses 0x00 and to 0x447

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Problem 0. The following table gives some of the parameters for a number of different hardware caches. Fill in the table with the values of the missing parameters. Recall that m is the number of physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity, i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Cache m 48 32030 (b) 48 32 24 24 C B E 16384 32 16 32768 64 65536 128 512 32 1024 8 8 4 14 1 4 S b S t
Consider the following portion of a page table from a system with 4 KiB (i.e., 4096 byte) pages. virtual page number physical page number 370 8 4 5 4. 37 5 3 Give the physical memory address of the byte with virtual memory address 12000. 2.
Consider a system with word-addressable memory in which a word is of 1 byte, 32-bit logical addresses memory, 2 kilobyte page size and page table entries of 4 bytes each. What is the size of the page table in the system in Mega word?
8.14. In the S/370 architecture, a storage key is a control field associated with each page- sized frame of real memory. Two bits of that key that are relevant for page replace- ment are the reference bit and the change bit. The reference bit is set to 1 when any address within the frame is accessed for read or write, and is set to 0 when a new page is loaded into the frame. The change bit is set to 1 when a write operation is per- formed on any location within the frame. Suggest an approach for determining which page frames are least-recently-used, making use of only the reference bit.
1. Write about the entire details of memory structure design and characteristics. 2. How much the number of bits calculation required for the logical address, if you considered the segment size is 1 k bytes and there are 32 segments? 3. In a paging model system, if a page size of 512 bytes and containing 64 entries of 11 bit each (including valid and invalid bit). How much the size of the physical address space needed?
Consider the following table that represents part of the memory of a 16-bit address space that has an addressability of 2 bytes (like LC-3): ADDRESS OxFFFF OXOCOE OXOCOD Ox0C0C OXOCOB OXOCOA 0x0C09 0x0000 CONTENTS 1111 1111 1111 1111 1111 1110 1101 1100 0001 1011 1100 0101 0110 0101 1000 0111 1100 0000 0100 0000 0011 0001 0101 0010 0000 1100 0000 1101 0000 0000 0000 0000 The table above shows the addresses in hex (base 16) and the contents at the corresponding address in binary (base 2). A.) What are the contents in hex of the memory location at following address in binary: 0000 1100 0000 1110? (Enter hex like the following example: Ox2A3F)
help with part A B AND C.
Explain the difference between a physical address, a segment address, and an offset address. What is the difference between non-overlapping memory segmentation and overlapping memory segmentation?
C1. Consider a main memory with size 4GB with cache size 16 KB and memory block is 8 bytes. Assume that the memory word is 1 byte. Answer the following questions: a. How many address bits are required to address the main memory locations? b. How many lines are there in the cache memory? c. Determine how to split the address (s-r, r, w) for direct mapping. d. Determine how to split the address (s-d, d, w) for set associative mapping. Assume each cache set is 2 lines of cache.
Suppose the page table for the process currently executing on the processor looks like the following. All numbers are decimal, everything is numbered starting from zero, and all addresses are memory byte addresses. The page size is 1024 bytes. Virtual page number 0 1 2 3 4 5 Valid bit 1 1 0 1 0 1 (ii) 2221 (iii) 5499 Reference bit 1 1 0 0 0 0 Modify bit 0 1 0 0 0 1 Page frame number 4 7 - 2 0 a. Describe exactly how, in general, a virtual address generated by the CPU is trans- lated into a physical main memory address. b. What physical address, if any, would each of the following virtual addresses corre- spond to? (Do not try to handle any page faults, if any.) (i) 1052
A typical computer system has a MM of size 4Gwords, and a 4-way cache memory of 256Kwords. The cache line size is 128words, while the cache miss penalty is 100 clock cycles. a) How many sets are in that cache? what is the tag size? b) Suppose the same cache described in part a is used, the CPU generates the following MM address to read an instruction from the MM in case of a cache miss. Address generated by CPU: n = #003EF6FH n= What would be the word number the CPU is requested? In which MM block this word should belongs to? Also, in which cache set this word and the whole MM block must be stored? e) If the cache hit time is 1 clock cycle, what is the hit rate would be required to achieve an AMAT equal to 3.86 clock cycle?
7. Consider a logical address space of 256 pages of 1024 words each. This is mapped onto a physical memory of 32 frames. How many bits are there in the logical and physical addresses?