4) Obtain the truth table for a 2-to-1 word-sized mux where the two input buses and output bus are all 2-bits wide. Use IN0_1, IN0_1, IN1_0, IN1_1, S for the inputs and OUT_0 and OUT_1 for the outputs. Obtain the schematic diagram for a possible implementation of such a mux following the example given in Figure 3.4.

Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter6: System Integration And Performance
Section: Chapter Questions
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4) Obtain the truth table for a 2-to-1 word-sized mux where the two input buses and output bus are
all 2-bits wide. Use IN0_1, IN0_1, IN1_0, IN1_1, S for the inputs and OUT_0 and OUT_1 for
the outputs. Obtain the schematic diagram for a possible implementation of such a mux following
the example given in Figure 3.4.
Transcribed Image Text:4) Obtain the truth table for a 2-to-1 word-sized mux where the two input buses and output bus are all 2-bits wide. Use IN0_1, IN0_1, IN1_0, IN1_1, S for the inputs and OUT_0 and OUT_1 for the outputs. Obtain the schematic diagram for a possible implementation of such a mux following the example given in Figure 3.4.
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