4) (a) What is the logic function implemented by the gate in Fig. P7.73? (b) Design the PMOS transis- tor network. Select the device sizes for both the NMOS and PMOS transistors to give a delay sim- ilar to that of the CMOS reference inverter. C is the same. (c) What is the equivalent W/L ratio of the NMOS switching network when all of the NMOS transistors are on? (d) Repeat for the PMOS network.

4) (a) What is the logic function implemented by the gate in Fig. P7.73? (b) Design the PMOS transis- tor network. Select the device sizes for both the NMOS and PMOS transistors to give a delay sim- ilar to that of the CMOS reference inverter. C is the same. (c) What is the equivalent W/L ratio of the NMOS switching network when all of the NMOS transistors are on? (d) Repeat for the PMOS network.

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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Question

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4)
(a) What is the logic function implemented by the
gate in Fig. P7.73? (b) Design the PMOS transis-
tor network. Select the device sizes for both the
NMOS and PMOS transistors to give a delay sim-
ilar to that of the CMOS reference inverter. C is
the same. (c) What is the equivalent W/L ratio
of the NMOS switching network when all of the
NMOS transistors are on? (d) Repeat for the PMOS
network.
+5 V
Logic
inputs
A to F
PMOS network
Y
E H
Figure P7.73

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J VDD RD - Vout You may have already noticed that the common source amplifier circuit is basically the same as the NMOS RTL inverter, just used for different purposes. The slope of the inverter VTC (Vout-Vin curve) is also the small- signal voltage gain of the common source amplifier. Assume VDD = 5V and Vin M₁ Vthn 0.7 V for the NMOS, use PSPICE to simulate the VTC (sweep from 0 to 5 V) of the common source amplifier for the following conditions: (a) Fix RD = 100 kN, L = 1 µm, W = 1 μm. Vary kn² = 20, 100, and 500 μА/V². (b) Fix kn' = 100 µA/V², R₁ = 100 kQ, L = 1 μm. Vary W = 1, 5, and 50 μm. (c) Fix kn' = 1 100 μA/V², L = 1 µm, W= 1 µm. Vary RD = 10 k2, 100 kQ, 1 MQ. Compare the slopes of the VTCs (which correspond to the voltage gains of the amplifiers) you obtained from the various conditions in a-c and explain your results.
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