For questions 1 through 3, use the following list of 32 bit memory address references, given as byte addresses.Note that you will need to convert them to binary: 3, 180, 43, 2, 191, 88, 190, 14, 180, 44, 186, 253 3. Assume a 2-way set associative cache with a 8 2-byte blocks. For each reference, list the binary address, the tag,the index, and if the reference is a hit or a miss, assuming the cache is initially empty.

Given data, 32 bit memory address Byte addresses: 3 180 43 2 191 88 190 14 180 44 186 253

3. Assume a 2-way set associative cache with a 8 2-byte blocks. For each reference, list the binary address, the tag, the index, and if the reference is a hit or a miss, assuming the cache is initially empty.

3. Assume a 2-way set associative cache with a 8 2-byte blocks. For each reference, list the binary address, the tag, the index, and if the reference is a hit or a miss, assuming the cache is initially empty.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Assume a cache of 1 MB organized as 32 bytes each line. The main memory is 256 MB. a. Determine the number of blocks in main memory b. Determine how to split the address (s-r, r, w) for direct mapping. c. Determine how to split the address (s, w) for associative mapping. d. Determine how to split the address (s-d, d, w) for set-associative each cache set is 4 lines of the cache.
Consider a 64K L2 memory and a 4K L1 2-way associative cache with block sizes of 512. a. How many blocks are in each set in L1? b. How many offset bits are in the L2 address? c. How many index bits are in the L2 address? d. How many tag bits are in the L2 address?
.2: Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 253 For each of these references, identify the binary address, the tag, and the index given a direct- mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 2-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 4-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
The following table gives the parameters for a number of different caches. For each cache, determine the number of cache sets (S), tag bits (t), set index bits (s), and block offset bits (b). Drag the appropriate labels to their respective targets. Note: not all labels will be used. Reset Help 1 0 2 3 4 5 6 7 8 9 10 15 11 12 13 20 21 22 24 27 28 29 30 31 32 38 48 128 218 256 Cache BE 1. 4 1 2. 8 4 3. 32 32 m C 32 1,024 32 1,024 32 1,024 S 1000 t 음 b 1000 1000 14 220
For a direct-mapped cache with 64KİB data, 8-word blocks, and 32-bit addresses, answer the following questions: a) What is the number of blocks/lines in the cache? b) Identify the bits in the 32-bit address that are used as index bits? c) Identify the bits in the 32-bit address that are used as tag bits? d) What is the total number of bits in this cache (including tag field and valid field)? e) Identify the block number in the cache to which the following 32-bit memory address maps: Ox00003Z00 (Hexadecimal notation) where Z is the least significant digit in your student ID (written as a decimal number)
We are given a list of 64-bit memory address references, given as word addresses. Ox03, Oxb4, Ox2b, 0x02, Oxbf, Ox58, Oxbe, OxOe, Oxb5, Ox2c, Oxba, Oxfd (A) For each of these references, identify the binary word address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list whether each reference is a hit or a miss, assuming the cache is initially empty. (B) For each of these references, identify the binary word address, the tag, the index, and the offset given a direct-mapped cache with two- word blocks and a total size of eight blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. (C) You are asked to optimize a cache design for the given references (i.e. addresses). There are three direct-mapped cache designs possible, all with a total of eight words of data: (i) Cache1 has 1-word blocks, (ii) Cache2 has 2-word blocks, and (iii) Cache3 has 4-word blocks.
A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
Below is a series of byte addresses in a system with 32 bit words. Assuming a direct-mapped cache with 4-word blocks and a total size of 32 words that is initially empty, (a) label each reference in the list as a hit or a miss and (b) show the entire history of the cache, including tag and data. Byte Address Byte Address (Hexadecimal) (Binary) Hit/Miss 76 0000 0000 0111 0110 1E3 0000 0001 1110 0011 815 0000 1000 0001 0101 141 0000 0001 0100 0001 170 0000 0001 0111 0000 5E1 0000 0101 1110 0001 320 0000 0011 0010 1100 B10 0000 1011 0001 0000 175 0000 0001 0111 0101 583 0000 0101 1000 0011 1FF 0000 0001 1111 1111 7A 0000 0000 0111 1010 2B2 0000 0010 1011 0010 5E4 0000 0101 1110 0100 816 0000 1000 0001 0110 438 0000 0100 0011 1000
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
Given an 8-word, 4-way set associative cache, and the sequence of address accesses below, enter the number of misses. 22 24 22 13 13 22
Suppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?
Consider a 32-bit physical memory space and a 32 KiB 2-way associative cache with LRU replacement. You are told the cache uses 5 bits for the offset field. Write in the number of bits in the tag and index fields. Tag length in bits = Index length in bits =