2. For a direct-mapped cache with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 00 Hex Dec 0 a) What is the cache block size (in words)? b) How many entries does the cache have? c) What is the ratio between total bits required for such a cache implementation over the data storage bits? Beginning from power on, the following byte-addressed cache references are recorded 04 4 Byte Address Index 9-5 Binary Address d) For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and (3) which bytes were replaced (if any). e) What is the hit ratio? Address 10 84 E8 AO 400 IE 8C CIC B4 884 16 132 232 160 1024 30 140 3100 180 2180 Offset 4-0 Tag Index Offset Hit/Miss Bytes Replaced
2. For a direct-mapped cache with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 00 Hex Dec 0 a) What is the cache block size (in words)? b) How many entries does the cache have? c) What is the ratio between total bits required for such a cache implementation over the data storage bits? Beginning from power on, the following byte-addressed cache references are recorded 04 4 Byte Address Index 9-5 Binary Address d) For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and (3) which bytes were replaced (if any). e) What is the hit ratio? Address 10 84 E8 AO 400 IE 8C CIC B4 884 16 132 232 160 1024 30 140 3100 180 2180 Offset 4-0 Tag Index Offset Hit/Miss Bytes Replaced
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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