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11- A TTL gate has the following actual voltage level values: VH(min) = 2.25 V, VILmax) = 0.65 V. Assuming it is being driven by a gate with VOH(min) = 2.4 V and VOL(max) = 0.4 V, what are the HIGH- and LOW-level noise margins? %3!

11- A TTL gate has the following actual voltage level values: VH(min) = 2.25 V, VILmax) = 0.65 V. Assuming it is being driven by a gate with VOH(min) = 2.4 V and VOL(max) = 0.4 V, what are the HIGH- and LOW-level noise margins? %3!

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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11- A TTL gate has the following actual voltage level values: VIH(min) = 2.25 V, VIL(max) = 0.65 V. Assuming it is being driven by a gate with VOH(min) = 2.4 V and VOL(max) = 0.4 V, what are the HIGH- and LOW-level noise margins? 12- What is the maximum amplitude of noise spikes that can be tolerated on the inputs in both the HIGH state and the LOW state for the gate in Problem 11? 2 mA in the LO pow delay time? Fora PHL 11. A standard TTL gate has a fan-out of 10. Are any of the gates in Figure 14-51 overloaded? If so, which ones? G6 Ao G10 G1 A1 G2 G3 Gg G11 X G4 G9 G5
Transcribed Image Text:11- A TTL gate has the following actual voltage level values: VIH(min) = 2.25 V, VIL(max) = 0.65 V. Assuming it is being driven by a gate with VOH(min) = 2.4 V and VOL(max) = 0.4 V, what are the HIGH- and LOW-level noise margins? 12- What is the maximum amplitude of noise spikes that can be tolerated on the inputs in both the HIGH state and the LOW state for the gate in Problem 11? 2 mA in the LO pow delay time? Fora PHL 11. A standard TTL gate has a fan-out of 10. Are any of the gates in Figure 14-51 overloaded? If so, which ones? G6 Ao G10 G1 A1 G2 G3 Gg G11 X G4 G9 G5
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