10.27. The widths of contact windows in certain CMOS circuit chips have a design specification of 3.5 um (see Phadke et al., The Bell System Technical Journal, 1983, for details.) Postetch window widths of test specimens were as follows: 3.21, 2.49, 2.94, 4.38, 4.02, 3.82, 3.30, 2.85, 3.34, 3.91 Can we reject the hypothesis that the design specification is being met, at the 5% significance level? What assumptions are necessary for this test to be valid?

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The widths of contact windows in certain CMOS circuit chips have a design specification of 3.5 μm (see Phadke et al., The Bell System Technical Journal, 1983, for details.) Postetch window widths of test specimens were as follows:

3.21, 2.49, 2.94, 4.38, 4.02, 3.82, 3.30, 2.85, 3.34, 3.91

Can we reject the hypothesis that the design specification is being met, at the 5% significance level? What assumptions are necessary for this test to be valid?l

10.27. The widths of contact windows in certain
CMOS circuit chips have a design specification
of 3.5 um (see Phadke et al., The Bell System
Technical Journal, 1983, for details.) Postetch
window widths of test specimens were as
follows:
3.21, 2.49, 2.94, 4.38, 4.02,
3.82, 3.30, 2.85, 3.34, 3.91
Can we reject the hypothesis that the
design specification is being met, at the 5%
significance level? What assumptions are
necessary for this test to be valid?
Transcribed Image Text:10.27. The widths of contact windows in certain CMOS circuit chips have a design specification of 3.5 um (see Phadke et al., The Bell System Technical Journal, 1983, for details.) Postetch window widths of test specimens were as follows: 3.21, 2.49, 2.94, 4.38, 4.02, 3.82, 3.30, 2.85, 3.34, 3.91 Can we reject the hypothesis that the design specification is being met, at the 5% significance level? What assumptions are necessary for this test to be valid?
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