1- What does the VOH parameter of a logic IC refer to?   a) The highest permissible output voltage. b) The lowest output voltage recognized as logic 1.   c) The highest output voltage recognized as logic 1.   d) The highest output voltage recognized as logic 0.

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1- What does the VOH parameter of a logic IC refer to?

 

a) The highest permissible output voltage. b) The lowest output voltage recognized as logic 1.

 

c) The highest output voltage recognized as logic 1.

 

d) The highest output voltage recognized as logic 0.

 

2- Which of the following refers to the noise margin of a logic gate?

 

a) The difference between VIH and VOL

 

b) The difference between VOH and VOL

 

c) The difference between VOH and VIH d) The difference between VIH and VIL

 

3- How many 74LS00 NAND gate inputs can be driven by a 74LS00 NAND

 

gate outputs Refer to data sheet of 74LS00, the maximum values of IOH = 0.4 mA, IOL = 8 mA, IH = 20 μA, and IL = 0.4 mA.

 

4- The data sheet of a quad two-input NAND gate specifies the following parameters: IOH (max.) 0.4 mA, VOH (min.) 2.7 V, VIH (min.) =2V, VIL (max.) 0.8 V, VOL (max.) 0.4 V, IOL (max.) 8 mA, IL (max.)=0.4 mA, IIH (max.)-20µA, ICCH (max.) 1.6 mA, ICCL (max.) 4.4 mA, tpLH =pHL=15 ns and a supply voltage range of 5 V. Determine (a) The average power dissipation of a single NAND gate,

 

(b) The maximum average propagation delay of a single gate, (c) The HIGH-state noise margin and (d) the LOW-state noise margin

 

5- Refer to exercise 4. How many NAND gate inputs can be driven from the output of a NAND gate of this type?

1- What does the VOH parameter of a logic IC refer to?
a) The highest permissible output voltage.
b) The lowest output voltage recognized as logic 1.
c) The highest output voltage recognized as logic 1.
d) The highest output voltage recognized as logic 0.
2- Which of the following refers to the noise margin of a logic gate?
a) The difference between VIH and VOL
b) The difference between VOH and VOL
c) The difference between VOH and VIH
d) The difference between VIH and VIL
3- How many 74LS00 NAND gate inputs can be driven by a 74LS00 NAND
gate outputs Refer to data sheet of 74LS00, the maximum values of IOH
%D
0.4 mA, IoOL = 8 mA, IH = 20 µA, and IL = 0.4 mA.
4- The data sheet of a quad two-input NAND gate specifies the following
parameters: IoH (max.)=0.4 mA, VOH (min.) =2.7 V, VIH (min.) =2V, VIL
(max.)=0.8 V, VOL (max.)=0.4 V, IOL (max.)=8 mA, IL (max.)=0.4 mA, IIH
(max.)=20µA, ICCH (max.)=1.6 mA, ICL (max.)=4.4 mA, tpLh =tpHL=15 ns
and a supply voltage range of 5 V. Determine
(a) The average power dissipation of a single NAND gate,
(b) The maximum average propagation delay of a single gate,
(c) The HIGH-state noise margin and (d) the LOW-state noise margin
5- Refer to exercise 4. How many NAND gate inputs can be driven from the
output of a NAND gate of this type?
Transcribed Image Text:1- What does the VOH parameter of a logic IC refer to? a) The highest permissible output voltage. b) The lowest output voltage recognized as logic 1. c) The highest output voltage recognized as logic 1. d) The highest output voltage recognized as logic 0. 2- Which of the following refers to the noise margin of a logic gate? a) The difference between VIH and VOL b) The difference between VOH and VOL c) The difference between VOH and VIH d) The difference between VIH and VIL 3- How many 74LS00 NAND gate inputs can be driven by a 74LS00 NAND gate outputs Refer to data sheet of 74LS00, the maximum values of IOH %D 0.4 mA, IoOL = 8 mA, IH = 20 µA, and IL = 0.4 mA. 4- The data sheet of a quad two-input NAND gate specifies the following parameters: IoH (max.)=0.4 mA, VOH (min.) =2.7 V, VIH (min.) =2V, VIL (max.)=0.8 V, VOL (max.)=0.4 V, IOL (max.)=8 mA, IL (max.)=0.4 mA, IIH (max.)=20µA, ICCH (max.)=1.6 mA, ICL (max.)=4.4 mA, tpLh =tpHL=15 ns and a supply voltage range of 5 V. Determine (a) The average power dissipation of a single NAND gate, (b) The maximum average propagation delay of a single gate, (c) The HIGH-state noise margin and (d) the LOW-state noise margin 5- Refer to exercise 4. How many NAND gate inputs can be driven from the output of a NAND gate of this type?
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