18.) Choose the 8088 signals that are used to generate ROMRD.a.) IORDb.) IO/Mc.) ALEd.) WRe.) RD Use the schematic for our board to select the input signals on the /O Memory selection hardware that are used to generate theIORD signal on our board.O RESETREADYO 10/MRDWRO WR

You have asked two different questions I think. First is related to 8088 ROMRD. and second is related IORD`In 8088 Memory Mapping the RAMRD, RAMWR, ROMRD, ROMWR, PC-RD and PC-WR bits are stored in the registers to specify the type of memory present at the memory region represented by the memory mapping registers, and also to specify the memory's access rights. When one of RAMRD, ROMRD, or PC-RD is asserted, the memory type is selected as RAM, ROM, or PC Card, respectively, and is enabled during Memory Read cycles. Any combination of RAMWR, ROMWR, or PC-WR may be enabled. Using this dual enable scheme (Read enable/Write enable), any region of the memory map may be defined as RAM, ROM, or PC Card. Furthermore, any region of the memory may be defined as read only, write only, read/write, or disabled. This allows RAM to shadow ROM, PC Cards to shadow RAM, or any combination of RAM/ROM/PC Cards. It also provides the ability for any or all of the memory map to be disabled (all Read enable and Write enable bits not asserted), so that external memory control logic may be utilized. ROMRD means we have selected ROM and are reading Data from it. So to generate IO/M should be be selected to Select memory , and RD should also be selected to show it is a read operation not a write operation. General example showing IO/M and RD signals required to generate MEMRD in general. We can generate Memory read and Memory Write using above logic.In IORD` that is IO read operation we need to read input from IO device . In Memory Mapped system we need to select IO/M` to be high to select IO (not memory) and also we should select RD` to be low so that active low read is selected. The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus. Ready signal is used to show device is ready for data transfer. SO to generate IORD ` IO/m` and RD` should be selected.