1-) Explain your codes step by step. How it works and what does your code do ? a.) 4-Bit Synchronous Parallel Load Shift Register with Counter and Asynchronous Reset: Write a Verilog code to read an 8-bit message from parallel input (user switches) into a shift-register, and use the shift function together with a counter to determine the number of '1's in the message (Don't use behavioral design instead used flip-flops). (no need for designing the 7-segment LED decoder here, the decoder will be used during the experimental work.) module countones (rst, Data, Clk,load,Q,Ones); input rst; input [7:0] Data; input Clk,load; output reg [3:0] Ones; output reg [7:0] Q; output reg [7:0] mask, temp; always@(posedge clk or negedge rst) begin if(!rst) begin Q<=8; Ones<=0; end else if (!clk) begin Q<=0; Ones<=0; end else if(load) begin Q<=Data; Ones<=0; end else if(!load) begin Q<=Data; Ones<=Data[3]; end end endmodule
1-) Explain your codes step by step. How it works and what does your code do ? a.) 4-Bit Synchronous Parallel Load Shift Register with Counter and Asynchronous Reset: Write a Verilog code to read an 8-bit message from parallel input (user switches) into a shift-register, and use the shift function together with a counter to determine the number of '1's in the message (Don't use behavioral design instead used flip-flops). (no need for designing the 7-segment LED decoder here, the decoder will be used during the experimental work.) module countones (rst, Data, Clk,load,Q,Ones); input rst; input [7:0] Data; input Clk,load; output reg [3:0] Ones; output reg [7:0] Q; output reg [7:0] mask, temp; always@(posedge clk or negedge rst) begin if(!rst) begin Q<=8; Ones<=0; end else if (!clk) begin Q<=0; Ones<=0; end else if(load) begin Q<=Data; Ones<=0; end else if(!load) begin Q<=Data; Ones<=Data[3]; end end endmodule
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question
![1-) Explain your codes step by step. How it works and what does your code do ?
a.)
4-Bit Synchronous Parallel Load Shift Register with Counter and Asynchronous Reset:
Write a Verilog code to read an 8-bit message from parallel input (user switches) into a shift-register, and
use the shift function together with a counter to determine the number of '1's in the message (Don't use
behavioral design instead use d flip-flops). (no need for designing the 7-segment LED decoder here, the
decoder will be used during the experimental work.)
module countones (rst, Data, Clk,load,Q,Ones);
input rst;
input [7:0] Data;
input Clk,load;
output reg [3:0] Ones;
output reg [Z:0] Q;
output reg [7:0] mask, temp;
always@(posedge clk or negedge rst)
begin if(!rst)
begin Q<=8; Ones<=0; end
else if (!clk) begin Q<=0; Ones<=0; end
else if(load)
begin
Q<=Data;
Ones<=0;
end
else if(!load)
begin
Q<=Data;
Ones<=Data[3];
end
end endmodule](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F57ddc131-d02f-4923-a2e9-17ad4597e1e5%2F1b6e6a8b-f50c-4a15-97aa-03b965a77c3e%2Fvmiqtka_processed.png&w=3840&q=75)
Transcribed Image Text:1-) Explain your codes step by step. How it works and what does your code do ?
a.)
4-Bit Synchronous Parallel Load Shift Register with Counter and Asynchronous Reset:
Write a Verilog code to read an 8-bit message from parallel input (user switches) into a shift-register, and
use the shift function together with a counter to determine the number of '1's in the message (Don't use
behavioral design instead use d flip-flops). (no need for designing the 7-segment LED decoder here, the
decoder will be used during the experimental work.)
module countones (rst, Data, Clk,load,Q,Ones);
input rst;
input [7:0] Data;
input Clk,load;
output reg [3:0] Ones;
output reg [Z:0] Q;
output reg [7:0] mask, temp;
always@(posedge clk or negedge rst)
begin if(!rst)
begin Q<=8; Ones<=0; end
else if (!clk) begin Q<=0; Ones<=0; end
else if(load)
begin
Q<=Data;
Ones<=0;
end
else if(!load)
begin
Q<=Data;
Ones<=Data[3];
end
end endmodule
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