a. Write True or False for each of the following statements 1. Q output follows T input at the triggering edge of the clock in T flip flop. 2. An encoder has at most 2" input lines and n output lines. 3. The binary code 0000 exhibits even parity. 4. A Demultiplexer has selection lines. 5. For a register with parallel data inputs, the bits are entered on a bit-by-bit basis on one line. 6. We can perform subtraction for binary numbers by taking the one's complement of the subtrahend and perform the addition with minuend. 7. The master and slave flip flops are triggered at the same time. 8. We can cascade two 2 x 4 decoders to build a 4 x 8 decoder that has no enable input. 9. Eight inputs data selector has three address input lines. 10. Decoders ICs can also be used in Demultiplexer applications.

Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
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a. Write True or False for each of the following statements
1. Q output follows T input at the triggering edge of the clock in T flip flop.
2. An encoder has at most 2" input lines and n output lines.
3. The binary code 0000 exhibits even parity.
4. A Demultiplexer has selection lines.
5. For a register with parallel data inputs, the bits are entered on a bit-by-bit basis on one line.
6. We can perform subtraction for binary numbers by taking the one's complement of the subtrahend and
perform the addition with minuend.
7. The master and slave flip flops are triggered at the same time.
8. We can cascade two 2 x 4 decoders to build a 4 x 8 decoder that has no enable input.
9. Eight inputs data selector has three address input lines.
10. Decoders ICs can also be used in Demultiplexer applications.
Transcribed Image Text:a. Write True or False for each of the following statements 1. Q output follows T input at the triggering edge of the clock in T flip flop. 2. An encoder has at most 2" input lines and n output lines. 3. The binary code 0000 exhibits even parity. 4. A Demultiplexer has selection lines. 5. For a register with parallel data inputs, the bits are entered on a bit-by-bit basis on one line. 6. We can perform subtraction for binary numbers by taking the one's complement of the subtrahend and perform the addition with minuend. 7. The master and slave flip flops are triggered at the same time. 8. We can cascade two 2 x 4 decoders to build a 4 x 8 decoder that has no enable input. 9. Eight inputs data selector has three address input lines. 10. Decoders ICs can also be used in Demultiplexer applications.
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