Q2) Answer one of the following A) Write a VHDL code to implement 3-state buffer shown below must provide output = input when ena (enable) is low, or output "zzzzzzzz" (high impedance) otherwise. input (7:0) output (7:0) B) Write a VHDL code to implement the comparator circuit between two numbers. a (n) ach

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
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Q2) Answer one of the following
A) Write a VHDL code to implement 3-state buffer shown below must
provide output= input when ena (enable) is low, or output
="Zzzzzzzz" (high impedance) otherwise.
ena
input (7:0)
output (7:0)
B) Write a VHDL code to implement the comparator circuit between
two numbers.
a tn0)
anb
ach
x3
Transcribed Image Text:Q2) Answer one of the following A) Write a VHDL code to implement 3-state buffer shown below must provide output= input when ena (enable) is low, or output ="Zzzzzzzz" (high impedance) otherwise. ena input (7:0) output (7:0) B) Write a VHDL code to implement the comparator circuit between two numbers. a tn0) anb ach x3
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